On the fly model checking of communicating UML State Machines1

In this paper we present the state/event-based temporal logic µUCTL which is a logic oriented towards a natural description of dynamic properties of UML models. This logic allows to specify the basic properties that a runtime system configuration should satisfy and to combine these basic predicates with logic and temporal operators which allow to take into consideration also the events performed by the system when evolving from one system configuration to another. Doubly Labelled Transition Systems are the semantic domain for µUCTL. The logic is supported by a prototypical verification environment under development at ISTI built around the "on the fly" UMC model checker. * Work partially founded by FET-IST 016004 project SENSORIA.

HAL (Le Centre pour la Communication Scientifique Directe), 2019

The increasing complexity of embedded systems renders verification of software programs more complex and may require applying monitoring and formal techniques, like modelchecking. However, to use such techniques, system engineers usually need formal experts to express software requirements in a formal language. To facilitate the use of model-checking tools by system engineers, our approach consists of using a UML model interpreter with which the software requirements can directly be expressed as observer automata in UML as well. These observer automata are synchronously composed with the system, and can be used unchanged both for model verification and runtime monitoring. Our approach has been evaluated on the user interface model of a cruise control system. The observer verification results are in line with the verification of equivalent LTL properties. The runtime overhead of the monitoring infrastructure is 6.5%, with only 1.2% memory overhead.

Refinement Techniques in Software Engineering, 2006

FM 2012: Formal Methods, 2012

This work presents a novel approach for the verification of Behavioral UML models, by means of software model checking. We propose adopting software model checking techniques for verification of UML models. We translate UML to verifiable C code which preserves the high level structure of the models, and abstracts details that are not needed for verification. We combine of static analysis and bounded model checking for verifying LTL safety properties and absence of livelocks. We implemented our approach on top of the bounded software model checker CBMC. We compared it to an IBM research tool that verifies UML models via a translation to IBM's hardware model checker RuleBasePE. Our experiments show that our approach is more scalable and more robust for finding long counterexamples. We also demonstrate the usefulness of several optimizations that we introduced into our tool.

Lecture Notes in Computer Science, 2004

We present a technique and a tool for model-checking operational UML models based on a mapping of object oriented UML models into a framework of communicating extended timed automata -in the IF format -and the use of the existing model-checking and simulation tools for this format. We take into account most of the structural and behavioral characteristics of classes and their interplay and tackle issues like the combination of operations, state machines, inheritance and polymorphism, with a particular semantic profile for communication and concurrency. The UML dialect considered here, also includes a set of extensions for expressing timing. Our approach is implemented by a tool importing UML models via an XMI repository, and thus supporting several commercial and non-commercial UML editors. For user friendly interactive simulation, an interface has been built, presenting feedback to the user in terms of the original UML model. Model-checking and model exploration can be done by reusing the existing IF state-of-the-art validation environment.

The paper presents a preliminary version of BMCU -a Bounded Model Checker for UML. All the executions of an UML system (unfolded to a given depth) are encoded into a boolean propositional formula, satisfiability of which is checked using a SAT-solver. Contrary to other UML verification tools we do not use any of the existing model checkers as we do not translate UML specifications into an intermediate formalism. The paper provides also preliminary experimental results.

2009

Programmable logic controllers (PLCs) are applied in a wide field of application and, especially, for safety-critical controls. Thus, there is the demand for high reliability of PLCs. Moreover, the increasing complexity of the PLC programs and the short time-to-market are hard to cope with. Formal verification techniques such as model checking allow for proving whether a PLC program meets its specification. However, the manual formalization of PLC programs is error-prone and time-consuming. This paper presents a novel approach to apply model checking to machine controls. The PLC program is modeled in form of Unified Modeling Language (UML) state-charts that serve as the input to our tool that automatically generates a corresponding formal model for the model checker NuSMV. We evaluate the capabilities of the proposed approach on an industrial machine control.

1991

Abstract A model-checking method for linear-time temporal logic that avoids the state explosion due to the modeling of concurrency by interleaving is presented. The method relies on the concept of the Mazurkiewicz trace as a semantic basis and uses automata-theoretic techniques, including automata that operate on words of ordinality higher than ω. In particular, automata operating on words of length ω× n, n∈ ω are defined.

2001

This paper presents an approach to model checking software system designs specified in xUML 9], an executable subset of UML. This approach is enabled by the execution semantics of xUML and is based on automatic translation from xUML to S/R [2], the input language of the COSPAN [2] model checker. Model transformations are applied to reduce the state space of the resulting S/R model that is to be verified by COSPAN. An xUML level logic for specifying properties to be checked is defined. Automated support is provided for translating properties specified in the logic to S/R representations and mapping error traces generated by COSPAN to xUML representations.

Science of Computer Programming, 2011

We present the UMC framework for the formal analysis of concurrent systems specified by collections of UML state machines. The formal model of a system is given by a doubly labelled transition system, and the logic used to specify its properties is the state-based and event-based logic UCTL. UMC is an on-the-fly analysis framework which allows the user to interactively explore a UML model, to visualize abstract behavioural slices of it and to perform local model checking of UCTL formulae. An automotive scenario from the serviceoriented computing (SOC) domain is used as case study to illustrate our approach.