Multicore compilation strategies and challenges

38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'05), 2005

Dynamic voltage and frequency scaling (DVFS) is an effective technique for controlling microprocessor energy and performance. Existing DVFS techniques are primarily based on hardware, OS timeinterrupts, or static-compiler techniques. However, substantially greater gains can be realized when control opportunities are also explored in a dynamic compilation environment. There are several advantages to deploying DVFS and managing energy/performance tradeoffs through the use of a dynamic compiler. Most importantly, dynamic compiler driven DVFS is fine-grained, code-aware, and adaptive to the current microarchitecture environment.

Lecture Notes in Computer Science, 2007

One of the key deliverables of the EU HiPEAC FP6 Network of Excellence is a roadmap on high-performance embedded architecture and compilation-the HiPEAC Roadmap for short. This paper is the result of the roadmapping process that took place within the HiPEAC community and beyond. It concisely describes the key research challenges ahead of us and it will be used to steer the HiPEAC research efforts. The roadmap details several of the key challenges that need to be tackled in the coming decade, in order to achieve scalable performance in multi-core systems, and in order to make them a practical mainstream technology for high-performance embedded systems. The HiPEAC roadmap is organized around 10 central themes: (i) single core architecture, (ii) multi-core architecture, (iii) interconnection networks, (iv) programming models and tools, (v) compilation, (vi) runtime systems, (vii) benchmarking, (viii) simulation and system modeling, (ix) reconfigurable computing, and (x) real-time systems. Per theme, a list of challenges is identified. In total 55 key challenges are listed in this roadmap. The list of challenges can serve as a valuable source of reference for researchers active in the field, it can help companies building their own R&D roadmap, and-although not intended as a tutorial document-it can even serve as an introduction to scientists and professionals interested in learning about high-performance embedded architecture and compilation.

2009

Abstract Multicore systems have not only become ubiquitous in the desktop and server worlds, but are also becoming the standard in the embedded space. Multicore offers programmability and flexibility over traditional ASIC solutions. However, many of the advantages of switching to multicore hinge on the assumption that software development is simpler and less costly than hardware development.

IEEE, 2024

Innovative, customizable computer architectures are driving significant advancements in performance for specific computation classes, such as dense matrix operations. However, compiling code for these new accelerators poses challenges, often requiring substantial engineering investment, particularly for tailored optimizations. In response, we are developing a compiler for a reconfigurable manycore architecture, leveraging program synthesis to distribute computation across a grid of simple processor cores. This approach eliminates the need for manual optimizations, streamlining spatial mapping. Our results show a remarkable 3.3-5.0X speedup in estimated cycle counts on microbenchmarks compared to single-core execution. Although scalability limitations are a concern, we have successfully compiled our largest microbenchmark, a 152-line code, within an hour, resulting in a non-optimal yet 1.7X faster partitioning. Our objective is to enable developers to harness efficient hardware accelerators without delving into low-level coding or waiting for the conventional development of optimized compilers. Moreover, this synthesis-based compiler technology is poised to offer enhanced flexibility for future, distinct yet related architectures.

2006 Innovations in Information Technology, 2006

The growing trend towards ubiquitous computing at handheld devices has brought the battery life time issue to the forefront. Scaling down the integrated circuit geometry has given rise to other issues e.g., leakage current and dynamic energy. Systems are software running on hardware; software directs the hardware components and is major contributor to the energy consumption. In this paper, we present compiler directed technique that take advantage of optimization slacks, scheduling slacks and linker slacks to optimize the dynamic energy consumption. Our framework is implemented in two phase. In first phase, profile of software application as well as underlying hardware is captured, followed by the code transformation in second phase. The optimization search engine is powered by genetic algorithm. We present results for 10 widely used multimedia applications, and analyze their behavior for parallelism, live CPU register usage, anticipated scheduling, CPU bus activity, processing units utilization and binary code size. Finally impact of these factors are studied on objective functions e.g., speedup, energy saving etc... Our result show that a unified scheme optimizes embedded source code better t han the conventional multiphase approaches in VLIW processors.

ACM Transactions on Embedded Computing Systems, 2012

Multicore architectures provide scalable performance with a lower hardware design effort than single core processors. Our paper presents a design methodology and an embedded multicore architecture, focusing on reducing the software design complexity and boosting the performance density. First, we analyze characteristics of the Task-Level Parallelism in modern multimedia workloads. These characteristics are used to formulate requirements for the programming model. Then, we translate the programming model requirements to an architecture specification, including a novel low-complexity implementation of cache coherence and a hardware synchronization unit. Our evaluation demonstrates that the novel coherence mechanism substantially simplifies hardware design, while reducing the performance by less than 18% relative to a complex snooping technique. Compared to a single processor core, the multicores have already proven to be more area-and energy-efficient. However, the multicore architectures in embedded systems still compete with highly efficient function-specific hardware accelerators. In this paper we identify five architectural methods to boost performance density of multicoresmicroarchitectural downscaling, asymmetric multicore architectures, multithreading, generic accelerators, and conjoining. Then, we present a novel methodology to explore multicore design spaces, including the architectural methods improving the performance density. The methodology is based on a complex formula computing performances of heterogeneous multicore systems. Using this design space exploration methodology for HD and QuadHD H.264 video decoding, we estimate that the required areas of multicores in CMOS 45 nm are 2.5 mm 2 and 8.6 mm 2 , respectively. These results suggest that heterogeneous multicores are cost-effective for embedded applications and can provide a good programmability support.

SSRN Electronic Journal, 2018

One of the most prevalent challenges of developing the future heterogeneous multicore systems is energy efficiency. Therefore, apart from performance, this paper proposes a high performance energy efficient analytical model for the combined heterogeneous parallel multicore system that is likely to be applied in big data applications. This model is extended by the traditional computer-centric model that considers the data preparation overhead that could not be neglected in the heterogeneous multicore processor system. This evaluation clearly demonstrates that the high levels of parallelism that have been gained from computation and data preparations result in high levels of energy efficiency. Enhancing the performance and energy efficiency of data preparation is a likely approach that may affect the consumption of power [1] Therefore, when developing the modern heterogeneous processor system, more informed tradeoffs that are within the energy budget limit should be considered.

Journal of Embedded Computing, 2005

The rapidly increasing number of architectural changes in embedded processors puts compiler technology under an enormous stress. This is emphasized by new demands on compilers, like requirements to reduce static code size, energy consumption or power dissipation. Iterative compilation has been proposed as an approach to find the best sequence of optimizations (such as loop transformations) for an application, in

micro, 1997

Compiler optimizations are often driven by specific assumptions about the underlying architecture and implementation of the target machine. For example, when targeting shared-memory multiprocessors, parallel programs are compiled to minimize sharing, in order to decrease high-cost, inter-processor communication.

2010

In this paper we try to determine which the major problems a developer is confronted with, when building an automatic parallel compiler for legacy code. Most of the code for multicore systems is generated from old, legacy sequential code and the process should be optimized so the time and resources spent adapting it are reduced. The article studies the work done so far and the main solution found in order to automatically parallelize the code. Because the operation is complex and the results are hard to be predicted, the interaction with the user is a necessity. Most of the existing tools for automatic parallelization solved the problem only for particular cases and others are just semi-automatic.