SystemJ compilation using the tandem virtual machine approach

Avinash Malik; Zoran Salcic; Partha S. Roop

doi:10.1145/1529255.1529256

Outline

SystemJ compilation using the tandem virtual machine approach

Avinash Malik

Zoran Salcic

2009, ACM Transactions on Design Automation of Electronic Systems

https://doi.org/10.1145/1529255.1529256

visibility

…

description

34 pages

link

1 file

Abstract

SystemJ is a language based on the Globally Asynchronous Locally Synchronous (GALS) paradigm. A SystemJ program is a collection of GALS nodes, also called clock domains and each clock domain is a synchronous program that extends the Java language. Initial compilation of SystemJ has been to standard Java executing on a Java Virtual Machine (JVM), which is both inefficient and bulky for small embedded systems. This paper proposes a new approach for compiling and executing SystemJ using a new type of virtual machine, called a Tandem Virtual Machine (TVM). The TVM approach provides an efficient implementation of SystemJ on both standard processors and resource constrained embedded processors. The new approach is based on separating the control-driven and data-driven operations for execution on two virtual machines. While the JVM executes the data-driven operations, a Control Virtual Machine (CVM) is introduced to execute the control-driven parts of a SystemJ program. The TVM approach is capable of handling all data-driven and control-driven operations required by the GALS model. The benchmark results show that the TVM has code size improvements of over 60% on average and also a substantial improvement in execution speed over standard Java based compilation.

Figures (17)

Fig. 2. Abstract view of an Engineering Calculator model in SystemJ
ACM Transactions on Design Automation of Electronic Systems, Vol. V, No. N, Month 20YY. — Fig. 2. Abstract view of an Engineering Calculator model in SystemJ ACM Transactions on Design Automation of Electronic Systems, Vol. V, No. N, Month 20YY.

Fig. 4. Example systemJ program with transition diagram for deadlock detection

Fig. 5. Example systemJ program with transition diagram for deadlock detection
The partial order sets for the two clock-domains in example Figure 5a are CD1 = — Fig. 5. Example systemJ program with transition diagram for deadlock detection The partial order sets for the two clock-domains in example Figure 5a are CD1 =

Fig. 6. GRC representation of the “UserNode reaction”

Fig. 7. AGRC representation of the server-client example
The GALS model of computation in SystemJ requires major extensions to the
GRC format. We introduce further nodes to represent channel, send/receive and — Fig. 7. AGRC representation of the server-client example The GALS model of computation in SystemJ requires major extensions to the GRC format. We introduce further nodes to represent channel, send/receive and

Fig. 8. Backend code generation and the grouping algorithm

also improves the runtime efficiency as pin pointing the memory location while
releasing data-locks becomes easier. Next the program counters (PC) for the various
synchronous reactions in a clock-domain are stored.
Fig. 9. Data memory layout for the CVM — also improves the runtime efficiency as pin pointing the memory location while releasing data-locks becomes easier. Next the program counters (PC) for the various synchronous reactions in a clock-domain are stored. Fig. 9. Data memory layout for the CVM

Table II. Selected special CVM instructions

ACM Transactions on Design Automation of Electronic Systems, Vol. V, No. N, Month 20YY.
SystemJ Compilation using the Tandem Virtual Machine Approach — ACM Transactions on Design Automation of Electronic Systems, Vol. V, No. N, Month 20YY. SystemJ Compilation using the Tandem Virtual Machine Approach

Figure 10 shows the communication interface between the CVM and the JVM.
As stated before we use a switch-case statement wrapped in a method for repre-
senting the various action-nodes (instantaneous data computations) which need to — Figure 10 shows the communication interface between the CVM and the JVM. As stated before we use a switch-case statement wrapped in a method for repre- senting the various action-nodes (instantaneous data computations) which need to

Fig. 11. ISR and the SENDATA flowcharts
be processed by the JVM. An 8-bit value is used for communication and to repre-
sent the case number (Section 4.4). The instruction SENDATA making the data
call provides the case number and a pointer into memory which holds the data lock
position (example, Table III CVM assembler source lines 1-3). CVM uses the DPC.
DPCR, and the IRQ registers to communicate with the JVM. The DPC register is
the control register which is set high to indicate to the JVM that a data-call request
has been made. The DPCR register at the same time contains the case number tc
be sent to the JVM. A currently executing data call is considered complete once the
IRQ register is set high by the JVM. Figure 11 shows the algorithms implemented
when a call to the JVM is made (SENDATA) and within the interrupt service
sequences (ISR). These algorithms perform sequences of atomic micro-operations
(register transfers). We utilize the Table III(c) lines 1-3, CVM source code lines tc
better explain the algorithms and the communication model. — Fig. 11. ISR and the SENDATA flowcharts be processed by the JVM. An 8-bit value is used for communication and to repre- sent the case number (Section 4.4). The instruction SENDATA making the data call provides the case number and a pointer into memory which holds the data lock position (example, Table III CVM assembler source lines 1-3). CVM uses the DPC. DPCR, and the IRQ registers to communicate with the JVM. The DPC register is the control register which is set high to indicate to the JVM that a data-call request has been made. The DPCR register at the same time contains the case number tc be sent to the JVM. A currently executing data call is considered complete once the IRQ register is set high by the JVM. Figure 11 shows the algorithms implemented when a call to the JVM is made (SENDATA) and within the interrupt service sequences (ISR). These algorithms perform sequences of atomic micro-operations (register transfers). We utilize the Table III(c) lines 1-3, CVM source code lines tc better explain the algorithms and the communication model.

Fig. 12. Environment communication model for the Tandem Virtual machine

Table IV. Characteristics of benchmarked examples: source code length, number of reactions and
number of clock-domains — Table IV. Characteristics of benchmarked examples: source code length, number of reactions and number of clock-domains

or the TVM is not as consistent as the code size gain. The run-time for TVM
varies from being ten times faster (cc example) to almost four times slower (aps
example). The current CVM uses Java native interface (JNI) to communicate with
che JVM for data-driven processing. JNI calls put a substantial over head on
‘un-time, so examples with a lot of such JNI calls (especially aps where calls are
nade to calculate each bit in a byte) are expected to have slower run-times. Even
with the JNI overhead, in general, the TVM performs better than the pure Java
mplementation. — or the TVM is not as consistent as the code size gain. The run-time for TVM varies from being ten times faster (cc example) to almost four times slower (aps example). The current CVM uses Java native interface (JNI) to communicate with che JVM for data-driven processing. JNI calls put a substantial over head on ‘un-time, so examples with a lot of such JNI calls (especially aps where calls are nade to calculate each bit in a byte) are expected to have slower run-times. Even with the JNI overhead, in general, the TVM performs better than the pure Java mplementation.

Table V. Run-time comparison, Pure Java Vs TVM
Fig. 13. Generated backend code size comparison between JVM and TVM — Table V. Run-time comparison, Pure Java Vs TVM Fig. 13. Generated backend code size comparison between JVM and TVM

References (28)

Berry, G. 1993. The Semantics of Pure Esterel. In Marktoberdorf Intl. Summer School on Program Design Calculi. LNCS. Springer-Verlag.
Berry, G. 1999. The Esterel v5 Language Primer -Version 5.10, release 2.0. Berry, G., Ramesh, S., and Shyamasundar, R. K. 1993. Communicating reactive processes. In POPL '93: Proceedings of the 20th ACM SIGPLAN-SIGACT symposium on Principles of programming languages. ACM Press, New York, NY, USA, 85-98.
Boussinot, F. and de Simone, R. 1996. The SL Synchronous Language. IEEE Trans. Softw. Eng. 22, 4, 256-266.
Boussinot, F. and Susini, J.-F. 1998. The sugarCubes tool box: a reactive Java framework. Softw. Pract. Exper. 28, 14, 1531-1550.
Butucaru, P. D. 2002. Optimisations for Faster Execution of Esterel Programs. Ph.D. thesis, Ecole des Mines de Paris.
Edwards, S. 2002. An Esterel compiler for large control-dominated systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 21, 2 (February), 169-183.
Edwards, S. 2006. Estbench Esterel Benchmark Suite. http://www1.cs.columbia.edu/ ∼ sedwards/software.html [Last Accesses: 22/09/2006].
Edwards, S. and Tardieu, O. 2006. SHIM: A Deterministic Model for Heterogeneous Embed- ded Systems. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION SYS- TEMS 14, 8 (August), 854-867.
Esterel Technologies SA. April 2003. Esterel Studio Reference Manual Version 4.2.
Gruian, F., Roop, P., Slacic, Z., and Radojevic, I. 2006. The SystemJ approach to System- Level Design. In The 4th International Conference on Formal Methods and Models for Code- sign(MEMOCODE).
Hazard, L., Susini, J.-F., and Boussinot, F. 1999. The Junior reactive kernel. In Research Report 3732. INRIA.
Hoare, C. A. R. 1985. Communicating Sequential Processes. Prentice Hall.
Kahn, G. 1974. The Semantics of Simple Language for Parallel Programming. In IFIP Congress. 471-475.
Lavagno, L. and Sentovich, E. 1999. ECL: A specification environment for system-level design. In Design Automation Conference. 511-516.
Li, X. and von Hanxleden, R. 2005. The Kiel Esterel Processor -A Semi-Custom, Configurable Reactive Processor. In Synchronous Programming -SYNCHRON'04, S. A. Edwards, N. Halb- wachs, R. v. Hanxleden, and T. Stauner, Eds. Number 04491 in Dagstuhl Seminar Proceedings. Internationales Begegnungs-und Forschungszentrum fuer Informatik (IBFI), Schloss Dagstuhl, Germany. <http://drops.dagstuhl.de/opus/volltexte/2005/159> [date of citation: 2005-01-01].
Malik, A. 2008. SystemJ Benchmark Suite. http://www.ece.auckland.ac.nz/ ∼ amal029 [Last Accesses: 09/11/2008].
Malik, A., Salcic, Z., and Roop, P. 2006a. Efficient Compilation of GALS Language-SystemJ. Tech. Rep. 655, University of Auckland.
Malik, A., Salcic, Z., and Roop, P. 2006b. SystemJ A GALS language for Embedded Systems and its Operational Semantics. Tech. Rep. 656, University of Auckland.
Malik, A., Salcic, Z., and Roop, P. S. 2008. An Efficient Execution Platform for GALS Lan- guage SystemJ. In The 13th IEEE Asia Pacific Computer Systems Architecture Conference.
Mandel, L. and Pouzet, M. 2005. ReactiveML: a reactive extension to ML. In PPDP '05: Proceedings of the 7th ACM SIGPLAN international conference on Principles and practice of declarative programming. ACM, New York, NY, USA, 82-93.
Murata, T., Shatz, S. M., and Shenker, B. 1989. Detection of Ada Static Deadlocks Using Petri Net Invariants. IEEE Trans. Softw. Eng. 15, 3, 314-326.
Plummer, B., Khajanchi, M., and Edwards, S. A. 2006. An Esterel virtual machine for em- bedded systems. In International Workshop on Synchronous Languages, Applications, and Programming (SLAP).
Ramesh, S. September, 1998. COMMUNICATING REACTIVE STATE MACHINES: DESIGN, MODEL AND IMPLEMENTATION. In IFAC Workshop on Distributed Computer Control Systems. Pergamon Press.
Salcic, Z., Hui, D., Roop, P., and Biglari-Abhari, M. 2005. REMIC: design of a reactive embedded microprocessor core. In ASP-DAC '05: Proceedings of the 2005 conference on Asia South Pacific design automation. ACM Press, New York, NY, USA, 977-981.
Salcic, Z. A., Roop, P., Biglari-Abhari, M., and Bigdeli, A. 2002. Reflix: A Processor Core for Reactive Embedded Applications. In FPL '02: Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications. Springer-Verlag, London, UK, 945-945.
Simon, Y., Hsien, Y. L., Sidharta, A., Partha, R., and Zoran, S. 2008. A New Multithreaded Architecture Direct Execution Platform for Esterel. In Model Driven high-level Programming of Embedded Systems SLA++P. European Joint Conference on Theory and Practice of Software. Budapest, Hungary.
Tardieu, O. and Edwards, S. A. 2006. Scheduling-independent threads and exceptions in SHIM. In EMSOFT '06: Proceedings of the 6th ACM & IEEE International conference on Embedded software. ACM Press, New York, NY, USA, 142-151.
Yoong, L., Roop, P., and Salcic, Z. 2006. Compiling Esterel for Distributed Execution. In Proceedings of Synchronous Languages, Applications and Programming.

SystemJ compilation using the tandem virtual machine approach

Sign up for access to the world's latest research

Abstract

Related papers

References (28)

Related papers

Related topics