New layer transfers obtained by the SmartCut process

Materials Science and Engineering: B, 2000

Ultra thin film of silicon bonded on 4 in. (001) silicon wafers have been obtained by combining a direct hydrophobic silicon bonded technique with a layer transfer. The twist angle between the ultra thin Si film and the Si substrate was varied from 0 to 15°. X-ray reflectivity measured the thickness and the roughness of the ultra thin films. Complementary results concerning the interface structure were obtained with high resolution transmission electronic microscopy. It is shown that an ultra thin film (a few nm) can be reproductively prepared upon the full 4 in. wafers. Moreover, this process gives very small thickness fluctuations and a small surface roughness. The bonding interface has a low concentration of oxide precipitates and presents two arrays dislocations respectively, due to the twist (screw dislocations) and a residual tilt angle (mixed dislocations) of the crystals. Dissociation of the screw dislocations is also observed on the lowest twist angle sample.

MRS Proceedings, 2004

ABSTRACTStrained Silicon On Insulator wafers are today envisioned as a natural and powerfulenhancement to standard SOI and/or bulk-like strained Si layers. For MOSFETs applications, thisnew technology potentially combines enhanced devices scalability allowed by thin films andenhanced electron and hole mobility in strained silicon. This paper is intended to demonstrate byexperimental results how a layer transfer technique such as the Smart Cut™ technology can be usedto obtain good quality tensile Strained Silicon On insulator wafers. Detailed experiments andcharacterizations will be used to characterize these engineered substrates and show that they arecompatible with the applications.

Journal of Electronic Materials, 2003

We demonstrate layer transfer of 150 nm of Si from a 200-mm, silicon-oninsulator (SOI) substrate onto a sapphire substrate using low-temperature wafer bonding (T ϭ 150°C). The crystalline quality and the thermal stability of the transferred Si layer were characterized by x-ray diffraction (XRD). A broadening of the (004) Si peak is observed only for anneal temperatures T A Ն 800°C, indicating some degradation of the crystalline quality of the transferred Si film above these temperatures. The measured electron Hall mobility in the bonded Si layer is comparable to bulk silicon for T A Յ 800°C, indicating excellent material quality.

Surface and Coatings …, 2009

Silicon oxynitride (Si x O y N z) buried layers were synthesized by high fluence (≥ 1 × 10 17 ions-cm − 2) ion implantation of O + and N + sequentially into single crystal silicon at 150 keV to produce silicon-on-insulator (SOI) structures. The structures of the SOI devices were analyzed by FTIR and XRD measurements and the surface modification by using atomic force microscopy (AFM). The FTIR measurements on the implanted samples (≤ 1× 10 18 ion-cm − 2) show a single absorption band in the wavenumber range 1300-750 cm − 1 attributed to the formation of silicon oxynitride bonds in silicon. The integrated absorption band intensity is found to increase with increase in the fluence. The samples with nitrogen-oxygen sequence of implantation showed nitrogen-rich oxynitride formation whereas samples with oxygen-nitrogen sequence resulted in oxygen-rich oxynitride. The formation of separate phases of Si-O and SiN bonds was observed at high fluence level (≅ 2 × 10 18 ions-cm − 2). The XRD studies show the formation of mixed phases of Si 2 N 2 O and SiO 2 in the sample. The structures of the ion beam synthesized silicon oxynitride layers are found to be strongly dependent on the sequence of implantation. The surface roughness is observed to be very small at lower fluences and it increases as we go to high fluence levels due to heavy damage caused by implantation. The conical hill like structures on the silicon surface is seen due to heavy surface swelling and sputtering phenomena.

Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, 2003

The notching ͑undercutting or footing͒ and stiction problem, which widely exists in silicon-on-insulator microstructure were resolved in this study regardless of the feature sizes, by the introduction of a spacer oxide thin film. In this modified process, the deep reactive ion etching was divided into several steps, where conformal plasma enhanced chemical vapor deposition oxide coating, and anisotropic oxide etch were employed to prevent the notching effect. Dry chemical release was also realized in this approach but the deep etching did not etch through the device layer. The notching or footing effect was exploited for attaining the lateral etching following the deployment of the anisotropic plasma etching of the inductively coupled plasma. This method was proven useful for both the uniform and nonuniform feature designs. To validate the proposed etching method, an optical switch was fabricated. The details and benefits of the proposed process and its extensions to more valuable and flexible design were all discussed in this article.

ECS Journal of Solid State Science and Technology, 2013

Physical and electrical characterization of thin doped silicon films is performed at different stage of low temperature layer transfer process. Spreading Resistance Profiling (SRP), Hall effect combined with Van der Pauw technique and standard I(V) measurements of p-n junctions are performed. Dopant deactivation above 95% is observed after hydrogen implantation and annealing at 500 • C is not enough to recover the initial doping level. A new and more effective process sequence, based on silicon amorphization and Solid Phase Epitaxy (SPE) at low temperatures, is applied after the layer transfer. Using this new process, the dopant activation of the transferred thin silicon film is completely recovered and the p-n diode forward current is improved by about 2 decades.

Materials Science and Engineering: B, 2006

Fabrication of strained silicon on insulator (sSOI) substrates by wafer bonding and layer splitting is described in this paper. The sSi layer of 20 nm thickness is obtained on an 8 in. virtual substrate that consists of a plastically relaxed SiGe layer grown epitaxially on Si(0 0 1) by chemical vapor deposition (CVD). The plastic relaxation of the initially pseudomorphic SiGe layer is mediated by helium implantation into the Si wafer below the SiGe/Si(0 0 1) interface and subsequent annealing. A SiO 2 layer is grown by plasma enhanced (PE) CVD on the sSi/virtual substrate prior to wafer bonding. The PECVD oxide layer is used to compensate the thermal stress existing at the bonding interface during annealing. The SiO 2 /sSi/virtual substrate wafers are then implanted with hydrogen at a high dose (3.5 × 10 16 H 2 + cm −2) and subsequently bonded to Si(0 0 1) handle wafers. Subsequent annealing of the bonded wafer pair leads to the transfer of the implanted layer (containing the sSi layer) from the virtual substrate to the Si handle wafer. The final sSOI structure is realized by subsequent chemo-mechanical polishing followed by selective wet chemical etching. The sSOI substrate shows good thickness uniformity (∼20 nm) of the sSi layer over the entire 8 in. area and the strain measurements indicate a value of ∼0.66%.

1998

The technology of the formation of SOIAS (Silicon-on-Insulator With Active Substrate) requires us to utilize the lower quality back side surface of the silicon film of the original Separation by Implantation of Oxygen (SIMOX) wafer. Transistor action occurs within a distance of approximately ten nanometers from the top silicon surface. This calls for an investigation and optimization of the surface properties of SOIAS. Novel chemical mechanical polishing (CMP) techniques were used to achieve surface roughness values as good as bulk silicon (2-3 Angstroms). Electrical parameters were determined by measuring the interface state density (Dit) using charge pumping, and the dielectric breakdown using time-zero breakdown (TZBD). The effective mobility (PEff) has been measured as a function of vertical electric field. Surface characterization was performed using atomic force microscopy (AFM). The relationship between surface roughness and these parameters has been determined by measuring the above electrical parameters on fabricated gated P-iN diodes and NMOS transistors with different surface roughness.

Journal of The Electrochemical Society, 2000

SiC is a wide bandgap semiconductor material with superior thermal, electrical, mechanical, and chemical properties for the fabrication of high temperature, high power, and high frequency electronic devices. In addition, it is also an excellent material for the fabrication of microelectromechanical systems (MEMS) devices that can operate at high temperatures and in high corrosion and radiation environments. The MEMS applications demand that large area, uniform SiC films be formed on structured sacrificial layers such as SiO 2 , Si 3 N 4 , and polycrystalline Si (poly-Si) for batch processing, which is essential in making SiC MEMS cost competitive. SiO 2 , Si 3 N 4 , poly-Si, or a stack of these films can be easily deposited or purchased commercially. Chemical vapor deposition (CVD) is an excellent tool for conformal growth on three-dimensional (3D) structures. SiC device definition and processing are well established. The main challenge is to grow SiC on these layers with reasonably high growth rate and low stress. The fabrication of such SiC semiconductor-on-insulator (SOI) structures first utilized sapphire substrates: direct deposition on sapphire, 1,2 SiC deposition on Si on sapphire (SOS), 3 and on AlN on sapphire, 4 and SiC growth on Si followed by removal of the substrate and attachment of the SiC film to a sapphire substrate. 5 The sapphire substrate approach was subsequently followed by the use of Si substrates to form SiC SOI on Si: carbonization of Si SOI followed by SiC growth, 6 wafer bonding, 7,8 and the Smart-Cut process. 9,10