HDL IP Cores Search Engine Based on Semantic Web Technologies

2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum, 2011

Superior and fast semantic comparison improves the quality of web-search. Semantic comparison involves dot product computation of large sparse tensors which is time consuming and expensive. In this paper we present a low power parallel architecture that consumes only 15.41 Watts and demonstrates a speed-up in the order of 10 5 compared to a contemporary hardware design, and in the order of 10 4 compared to a purely software approach. Such high performance low power architecture can be used in semantic routers to elegantly implement energy efficient distributed search engines.

1998

JHDL is a design tool for reconfigurable systems that allows designers to express circuit organizations that dynamically change over time in a natural way, using only standard programming abstractions found in objectoriented languages. JHDL manages FPGA resources in a manner that is similar to the way object-oriented languages manage memory: circuits are treated as distinct objects and a circuit is configured onto a configurable computing machine (CCM) by invoking its constructor, effectively "constructing" an instance of the circuit onto the reconfigurable platform just as object instances are allocated in memory with conventional object-oriented languages. This approach of using object constructors/destructors to control the circuit lifetime on a CCM is a powerful technique that naturally leads to a dual simulation/execution environment where a designer can easily switch between either software simulation or hardware execution on a CCM with a single application description. Moreover, JHDL supports dual hardware/software execution; parts of the application described using JHDL circuit constructs can be executed on the CCM while the remainder of the application -the GUI for example-can run on the CCM host. Based on an existing programming language (Java), JHDL requires no language extensions and can be used with any standard Java 1.1 distribution.

EURASIP Journal on Embedded Systems, 2008

HercuLeS is an extensible high-level synthesis (HLS) environment. It removes significant human effort by automatically mapping algorithms to hardware, providing a valuable design assist to software-oriented developers. To enable accessibility and easiness of hardware design space exploration (DSE), HercuLeS overcomes limitations of known work: non-standard source languages, insufficient representations, maintenance difficulties, necessity of code templates, lack of usage paradigms and vendor-dependence. Specific aspects that are highlighted in this manuscript are: a) the innerworkings of the HercuLeS hardware compilation engine, b) manipulation of SSA (Static Single Assignment) form, c) automatic third-party IP integration, d) backend C code generation for compiled simulation, and e) an exemplary case of DSE. HercuLeS enables efficient hardware generation that can closely match the quality of results of a manuallydeveloped implementation with much reduced human effort and time requirements.

1989

International Journal of Computers and Communications, 2021

Intellectual Properties reuse has gained widespread acceptance in System-On-Chip design to manage the complexity and shorten the time-to-market. However the need for a standard representation that permits IPs classification, characterization, and integration is still a big challenge. To address this problem, we propose to develop an IPs reuse specific ontology that facilitates IPs reuse at many levels of abstraction and independently from any design language or tool. Our ontology is built using the Protégé-OWL tool

1992

The semantics of hardware description languages can be represented in higher order logic. This provides a formal de nition that is suitable for machine processing. Experiments are in progress at Cambridge to see whether this method can be the basis of practical tools based on the HOL theorem-proving assistant. Three languages are being investigated: ELLA, Silage and VHDL. The approaches taken for these languages are compared and current progress on building semantically-based theorem-proving tools is discussed.

2010

Increasingly complex embedded systems are being designed onto single chip systems that contain multiple parallel processing elements and memories. The design and implementation of these multiprocessor on-chip architectures is time consuming, delaying the time to market. Manual hardware design is also error-prone, requiring careful verification and further delaying the time to market. In order to solve the aforementioned problems, an open source VHDL generation tool called SING was created to design and implement heterogeneous multiprocessor system-on-chip designs. The requirements for the tool which are partially or fully addressed are: 1. use of existing and open-source components, 2. automated generation of VHDL, 3. Eclipse framework, and 4. simulation capabilities. The tool comes with a graphical user interface (GUI) and an application programmer interface (API), and exports VHDL with accompanying documentation in accordance with the WISHBONE B.3 standard. The exported VHDL can then be prototyped on an FPGA platform. Even though some similar tools exist, there are not many papers that present detailed internal design of the tools. We believe that our detailed description of the object oriented implementation will be helpful to designers of similar systems.

Proceedings 20th IEEE International Parallel & Distributed Processing Symposium, 2006

This paper aims at introducing a methodology that allows an easy implementation of IP-Cores focusing only on their functionalities rather than their interfaces and their integration in a given architecture. The proposed approach implements all the communication infrastructure needed by a component, described in VHDL, to be finally inserted into a real architecture that can be implemented on FPGAs, reducing the time to market of the final implementation of the system. To validate the entire methodology, we have performed a comparison based on the CoreConnect communication infrastructure, between our results with the classical Xilinx design flow using EDK and ISE.

The Multimedia Home Platform (MHP) standard provides a technical specification of a wide range of terminals (Set-Top-Boxes) for digital video broadcasting (DVB) that enable the interaction of the end user by means of JAVA and HTML based applications. This paper presents an MHP reference implementation in which an extra abstraction layer for the hardware resources is defined. This layer consists of dual interfaces providing the rest of the reference implementation with a set of reusable software components controlling all the hardware resources.