Mapping Concurrent Applications onto Architectural Platforms

ACM Transactions on Design Automation of Electronic Systems, 2009

A growing number of applications, often with firm or soft real-time requirements, are integrated on the same System on Chip, in the form of either hardware or software intellectual property. The applications are started and stopped at run time, creating different use-cases. Resources, such as interconnects and memories, are shared between different applications, both within and between use-cases, to reduce silicon cost and power consumption.

Proceedings of the 38th conference on Design automation - DAC '01, 2001

Communication-based design represents a formal approach to systemon-a-chip design that considers communication between components as important as the computations they perform. Our "network-on-chip" approach partitions the communication into layers to maximize reuse and provide a programmer with an abstraction of the underlying communication framework. This layered approach is cast in the structure advocated by the OSI Reference Model and is demonstrated with a reconfigurable DSP example. The Metropolis methodology of deriving layers through a sequence of adaptation steps between incompatible behaviors is illustrated through the Intercom design example. In another approach, MESCAL provides a designer with tools for a correct-by-construction protocol stack.

2001

Abstract System level design is complex. One source of this complexity is that systems are often heterogeneous: different models of computation (eg, dataflow, FSMs) are used to describe different components of a system. Existing formal methods for concurrent systems are typically based on one particular model of computation, so it is difficult to formalize the interaction between heterogeneous components. In this paper, we develop a framework for formalizing the relationships between different models of computation

2007

In this paper we present a survey of a recently developed approach to specifying, modelling, exploring and designing parallel media-processing and wireless communications platforms and platform instances. More specifically, we take a closer look at the notions of Y-chart and Abstraction Pyramid. The methodology and approach that is reviewed in this paper uses these notions and focuses on the system level of abstraction on which the application and the architecture are co-existing in terms of a Model of Computation and a Model of Architecture, respectively. The relation between the two models is expressed in terms of a mapping layer with transformation methods that take a particular representation of (parts of) the application model and bind it to a particular representation of (parts of) the architecture model, and all this in such a way that: 1) modifications in either the application, or the architecture, or the mapping can be easily dealt with (for exploration purposes) , 2) the ...

Design Automation for Embedded Systems, 2002

Virtuoso VSP is a fully distributed real-time operating system originally developed on the Inmos transputer. Its generic architecture is based on a small but very fast nanokernel and a portable preemptive microkernel. It was further on ported in single and virtual single processor implementations to a wide range of processors. This paper describes the rationale for developing the distributed semantics of Virtuoso's microkernel and describes some of the implementation issues. The analysis is based on the parallel DSP implementations as these push the performance limits most for hard real-time applications. Extensions of the model towards heterogeneous embedded target systems are discussed.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2000

The MultiFlex system is an application-to-platform mapping tool that integrates heterogeneous parallel components-H/W or S/W-into a homogeneous platform programming environment. This leads to higher quality designs through encapsulation and abstraction. Two high-level parallel programming models are supported by the following MultiFlex platform mapping tools: a distributed system object component (DSOC) object-oriented message passing model and a symmetrical multiprocessing (SMP) model using shared memory. We demonstrate the combined use of the MultiFlex multiprocessor mapping tools, supported by high-speed hardware-assisted messaging, context-switching, and dynamic scheduling using the StepNP demonstrator multiprocessor system-on-chip platform, for two representative applications: 1) an Internet traffic management application running at 2.5 Gb/s and 2) an MPEG4 video encoder (VGA resolution, at 30 frames/s). For these applications, a combination of the DSOC and SMP programming models were used in interoperable fashion. After optimization and mapping, processor utilization rates of 85%-91% were demonstrated for the traffic manager. For the MPEG4 decoder, the average processor utilization was 88%.

IEEE Design & Test of Computers, 2001

THE ADOPTION OF SYSTEM-ON-A-CHIP (SOC) architectures in future embedded-system designs will bring many advantages in terms of performance, cost, reliability, power consumption, and system size. However, to fully benefit from those advantages, designers must fine-tune the SOC architecture to suit application-specific characteristics and requirements. An application-specific multiprocessor SOC architecture (ASMSA) constitutes an ideal hardware platform since, in theory, it can be configured to fit the application's needs exactly. Such architectures allow many customizations. One of the most important design decisions is the topology and protocols chosen for communication between processors, memories, and peripherals. Achieving optimal ASMSA customization for complex applications is an overwhelming task because customizations are interdependent. Most researchers agree that independently refining communication and system behavior is a good strategy to reduce system design complexity and to achieve solutions that are sufficiently close to optimal. 1 This strategy leads naturally to a design flow in which the communication infrastructure and application code customizations follow independent paths during mapping of the system specification into an ASMSA. 2 The designer can perform these customizations concurrently if the design model separates communication and computation. A design representation for automating the ASMSA design flow must take these issues into account. The choices we have mentioned imply many trade-offs between design complexity, system performance, degree of automation, verification, and design reuse. A design model targeted at efficient ASMSA synthesis must support three main features: I Flexible communication modeling. The intrachip communication network must be modeled flexibly because application-specific optimizations might lead to a very complex architecture in which multiple topologies and protocols coexist. Furthermore, for flexibility's sake, communication models must not

International Journal of Online and Biomedical Engineering (iJOE), 2019

It is common knowledge in Information Technology (IT) that an embedded system is based on microprocessor and is built to control a function or a range of functions. Although, it is not designed to be programmed by the end user in the same way that a PC is, it is designed to perform one particular task with choices and different options [1-5]. Multitasking is a method by which multiple tasks, also known as processes, share common processing resources, such as CPU. The main aim of this paper is analysis of the design of the embedded systems and a focus on mid-level abstractions for concurrent programs.

Proceedings of the 43rd annual conference on Design automation - DAC '06, 2006

For the design of classic computers the Parallel programming concept is used to abstract HW/SW interfaces during high level specification of application software. The software is then adapted to an existing multiprocessor platforms using a low level software layers that implement the programming model. Unlike classic computers, the design of heterogeneous MPSoC includes also building the processors and other kind of hardware components required to execute the software. In this case, the programming model hides both hardware and software refinements. This paper deals with parallel programming models to abstract both hardware and software Interfaces in the case of heterogeneous MPSoC design. Different abstraction levels will be needed. For the long term, the use of higher level programming models will open new vistas for optimization and architecture exploration like CPU/RTOS tradeoffs.

ACM SIGBED Review, 2014

As embedded systems need more and more computing power, many products require hardware platforms based on multiple processors. In case of real-time constrained systems, the use of scheduling analysis tools is mandatory to validate the design choices, and to better use the processing capacity of the system.