An Optimal Design of Reversible Fault Tolerant n Bit Comparator

In this paper, we propose an n-bit reversible fault tolerant binary division circuit, where n is the number of bits of dividend and divisor. We present a new algorithm for division operation with the optimum time complexity in the design of dividers. The proposed division method consists of four steps: Firstly, it considers floating-point data and rounding. Secondly, it performs correctly rounded division. Thirdly, it performs correct rounding from one sided approximations. Finally, it calculates the result of the division operation. The proposed design of the divider circuit shows that it is composed of reversible fault tolerant multiplexers, parallel-in–parallel out (PIPO) left shift registers, D-Latch, rounding and normalization registers and parallel adder. The proposed divisor register and the parallel adder have the minimum quantum cost with respect to the existing ones. Fredkin gates and Feynman double gates are also used to form the divider circuit. Finally, we present an algorithm to construct a compact n-bit reversible fault tolerant binary division circuit. In this paper, a new algorithm has also been proposed to reduce the number of steps required for performing division operation. Our circuit performs better than the existing approaches considering all the efficiency parameters of reversible logic design which includes number of gates, constant inputs, garbage outputs, quantum cost and delay of the circuit, e.g., for a 256-bit binary division circuit, the proposed reversible fault tolerant binary division circuit improves 27.75% on the number of gates, 0.03% on garbage outputs, 11.04% on quantum cost, 8.94% on constant inputs and 23.50% on delay with respect to the best known existing divider circuit. We also simulate the proposed n-bit reversible fault tolerant binary division circuit using Microwind DSCH 3 which shows the correctness of the circuit.

In digital electronics, the power dissipation is the major problem. So that the reversible gate can be implemented in microelectronics and electronics which have low power dissipation in the digital designing because, in the reversible state in reversible logic it will use no energy. Hence reversible logic has ability to reduce the power dissipation in digital designing. In the Reversible logic, reversibility have a special condition which is reversible computing and reversible computing is based on the principle of BIJECTION DEVICE with a same no. of input and output which means one to one mapping. Reversible logic has numerous applications in the field of electronics and microelectronics which are ultra low power in nanoscale computing, quantum computing, emerging nanotechnology cellular automata and the other approach of reversible logic is ballistic computation, mechanical computation which are the basic technology. This paper presents an optimization of reversible comparator using the existing reversible gates and proposed new Reversible one bit comparator using BVF gate. A comparative result is presented in terms of number of gates, number of garbage outputs, number of constant inputs and Quantum cost.

TENCON 2007 - 2007 IEEE Region 10 Conference, 2007

In recent years, reversible logic has emerged as one of the most important approaches for power optimization with its application in low power CMOS, quantum computing and nanotechnology. Low power circuits implemented using reversible logic that provides single error correction -double error detection (SEC-DED) is proposed in this paper. The design is done using a new 4 x 4 reversible gate called 'HCG' for implementing hamming error coding and detection circuits. A parity preserving HCG (PPHCG) that preserves the input parity at the output bits is used for achieving fault tolerance for the hamming error coding and detection circuits.

2012

Since the Arithmetic Logic Unit (ALU) is one of the essential components of the Central Processing Unit (CPU), its well performance is the most important factor in obtaining the high reliability. The reversible logic has also found emerging attention in nanotechnology, optical computing, quantum computing and low power CMOS design. In this paper we are going to propose and analyze a basic model of fault tolerant reversible ALU and show that the realization of an efficient fault tolerant reversible ALU is possible with both minimum constant inputs and garbage outputs. The proposed fault tolerant reversible ALU is a versatile approach to the implementation of quantum computing with having both a remarkable low power consumption and nano scaling.

Reversible circuits have applications in digital signal processing, computer graphics and cryptography. They are also a fundamental requirement in the field of quantum computation. We investigate the synthesis of reversible circuits that employ a minimum number of gates and contain no redundant input-output line pairs. In this paper, we have proposed a structure which constructs Reversible Programmable Array Logic (RPAL) as well as the RPAL is Fault Tolerant. An algorithm has been proposed to reduce total number of gates and garbage outputs in the AND plane of a RPAL. We compare the existing AND plane of Reversible Programmable Logic Array (RPLA) with the proposed one using benchmark functions. Our proposed design can realize ESOP (Exclusive Sum-of-Products) operations in terms of multi-output functions by using minimum number of gates, garbage outputs and quantum costs. In our design, we have used fault tolerant FRG (Fredkin Gate) and F2G (Feynman Double Gate) for making our RPAL Fault Tolerant. We have also proposed a fault tolerant design for RPAL in the OR plane with the minimum number of gates, garbage outputs and quantum costs. A Reversible Gate named FEG (Feynman Extension Gate) is also proposed to show the compactness of the proposed OR plane.

International Journal of Modern Education and Computer Science, 2016

Demand of reliable computing has been a major concern since the dawn of the electronic digital computer age. Reliable computing has various applications not only in the field of military, aerospace and communication but even contemporary commercial applications to fulfill today's automated life style. The tremendous growth in fabrication from small scale integration (SSI) to giant scale integration (GSI) is facing power dissipation as one of the main barriers. To overcome this barrier, researchers need to enter into the reversible logic domain. Making a reversible circuit robust or fault tolerant is much more difficult than a conventional logic circuit. Fault tolerance can be achieved in a system by using parity bits. The main aim of this paper is to come up with a new fault tolerant ALU design based on parity preserving reversible logic gates with improved quantum cost and power overhead as compare to existing fault tolerance based ALU designs. The most stringent requirement for fault tolerant ALU is in real time control system where faulty computation jeopardizes human life or other catastrophic effects.Implentation of proposed design is done using Xilinx ISE design suit 14.2 tool and its performance over existing ALU designs is qualitatively analyzed.

International Journal of Computer Applications, 2014

Fault Tolerant reversible decoders are the prerequisite of high performance computing systems. In this paper, an optimized reversible fault tolerant decoder has been proposed by using novel cost effective gates named Reversible Fault Tolerant Decoder (RDC) and Double Fredkin Gate (DFG). Several lower bounds on the numbers of gates, garbage and quantum costs are also proposed to generalize the architecture of n-to-2 n reversible decoder. The comparative performance analysis shows that the proposed design outperforms the existing designs in terms of number of gates used, quantum cost, delay, ancilla inputs and design complexity.

International Journal of VLSI Design & Communication Systems, 2013

Nowadays exponential advancement in reversible computation has lead to better fabrication and integration process. It has become very popular over the last few years since reversible logic circuits dramatically reduce energy loss. It consumes less power by recovering bit loss from its unique input-output mapping. This paper presents two new gates called RC-I and RC-II to design an n-bit signed binary comparator where simulation results show that the proposed circuit works correctly and gives significantly better performance than the existing counterparts. An algorithm has been presented in this paper for constructing an optimized reversible n-bit signed comparator circuit. Moreover some lower bounds have been proposed on the quantum cost, the numbers of gates used and the number of garbage outputs generated for designing a low cost reversible signed comparator. The comparative study shows that the proposed design exhibits superior performance considering all the efficiency parameters of reversible logic design which includes number of gates used, quantum cost, garbage output and constant inputs. This proposed design has certainly outperformed all the other existing approaches.

2012 IEEE Computer Society Annual Symposium on VLSI, 2012

Programmable reversible logic is gain wide consideration as a logic design style for modern nanotechnology and quantum computing with minimal impact on circuit heat generation in improved computer architecture and arithmetic logic unit designs. In this paper, a 2*2 Swap gate which is a reduced implementation in terms of quantum cost and delay to the previous Swap gate is presented. Then, a novel 3*3 programmable UPG gate capable of calculating the universal logic calculations is presented and verified, and its advantages over the Toffoli and Peres gates are discussed. The UPG is then implemented in a reduced design for calculating n-bit AND, n-bit OR and n-bit ZERO calculations. Then, two 3*3 RMUX gates capable of multiplexing two input values with reduced quantum cost and delay compared to the previously existing Fredkin gate is presented and verified. Next, a novel 4*4 reversible programmable RC gate capable of nine unique logical calculations at low cost and delay is presented and verified. The UPG and RC are implemented in the design of novel sequential and tree-based comparators. These designs are compared to previously existing designs, and their advantages in terms of cost and delay are analyzed. Then, the RMUX is used to improve a reversible SRAM cell we previously presented. The memory cell and comparator are implemented in the design of a Min/Max Comparator device.

IOP Conference Series: Materials Science and Engineering, 2017

Multiplier is one of the essential component in the digital world such as in digital signal processing, microprocessor, quantum computing and widely used in arithmetic unit. Due to the complexity of the multiplier, tendency of errors are very high. This paper aimed to design a 2x2 bit Fault Tolerance Multiplier based on Reversible logic gate with low power consumption and high performance. This design have been implemented using 90nm Complemetary Metal Oxide Semiconductor (CMOS) technology in Synopsys Electronic Design Automation (EDA) Tools. Implementation of the multiplier architecture is by using the reversible logic gates. The fault tolerance multiplier used the combination of three reversible logic gate which are Double Feynman gate (F2G), New Fault Tolerance (NFT) gate and Islam Gate (IG) with the area of 160µm x 420.3µm (67.25 mm²). This design achieved a low power consumption of 122.85µW and propagation delay of 16.99ns. The fault tolerance multiplier proposed achieved a low power consumption and high performance which suitable for application of modern computing as it has a fault tolerance capabilities.