Voiding Control for QFN Assembly

Proceedings of the 1996 Asian Conference on X-Rays and Related Techniques in Research and Industry (ACXRI'96), 1996

Solder voids are believed to cause poor heat dissipation in the Surface Mount devices and reduce the reliability of the devices at higher operating services. There are a lot of factors involved in creating voids such as gas/flux entrapment, wettability, outgasses, air bubbles in the solder paste, inconsistency of solder coverage and improper metal scheme selection. This study was conducted in order to observe the behavior of the solder voids in term of flux entrapment and wettability. It is believed that flux entrapment and wettability are verifying this hypothesis. Two types of metal scheme were chosen which are Nickel (Ni) plated and Tin (Sn) plated heatsink. X-ray techniques such as Radiographic Inspection Analysis and EDX were used to detect the minute solder voids. The solder voids observed on the heatsinks and Copper shims after the reflow process are believed to be a non-contact voids that resulted from some portion of the surface not wetting properly.

Applied Thermal Engineering, 2018

Process-induced solder voids have three-dimensional shapes and show spatially random distribution with polydisperse geometric dimensions. There exists no analytical formulation of thermal resistances which incorporates void shapes, distribution and polydispersity variables. This paper uses finite element methods to investigate the effect of realistic void morphology on the thermal resistance of solder thermal interface materials (STIMs). The study has developed two computationally efficient methods for generating voids that show the features of real voids. Cylindrical and spherical void morphologies have been studied. The study is the first attempt, in literature, of characterizing the holistic effects of such realistic three-dimensional void morphologies on the thermal resistance of STIM layers. We have shown a qualitative agreement between our results and simplistic analytical predictions. However, the influence of void shapes, distribution and polydispersity have been shown to contribute to increased thermal resistances. The findings should provide significant insight to electrical/electronics engineers, microelectronics chips manufacturers and academic research groups working on thermodynamics design of chip scale package (CSP) devices. It is also a framework for investigating objectively, the consequence of voids on the thermomechanical response of solder joints.

Applied Thermal Engineering, 2014

An algorithm used to generate RVEs depicting the randomness of voids in STIM layers. Generated 2D RVEs converted to 3D RVEs within finite element modelling environment. 3D RVEs incorporated into chip and heat spreader to complete the geometrical set-up. Parametric studies on the STIM layer due to the generated void morphology performed. Results showed voids can influence the initiation or propagation of damage in STIM.

An approach based on design of different experiments for improvement the thermal paths in PCB through thermal vias is offered. An efficient thermal via placed on the PCB decreases the junction temperature of the package. In this paper elaborate study has been done in analyzing the effect of thermal vias and the ways to decrease the junction temperature by given number of computations. Thermal enhancement has been achieved by running the thermal simulations with and without thermal vias. Temperature profiles have been plotted in FLOTHERM. The thermal enhancement study focuses on the importance of thermal vias to a great extent. The simulation models are validated with experiments.

2018

A special thanks to Dr. Agonafer for giving me this opportunity and let me join his outstanding reliability team. His excellent guidance taking me to the end of this study for which I will always be grateful. I would like to thank my family for always supporting me throughout this master's journey and for always being there for me. I would also like to thank Dr. A. Haji-Sheikh and Dr. Fahad Mirza for being on the Committee for my thesis defense. I owe this to Mr. Pavan Rajmane and Mr. Unique Rahangdalefor guiding me through this and mentoring all the way along. I appreciate my team members Samuel Ambosta and Anuraag Karnik for helping me out whenever required. Finally, I would like to thank my roommates for being new family away from home. Special thanks to Rohit Nikam, Samruddhi Ghumre, Omkar Pawar, Bhagyesh Raut for standing by me in all my decisions and be pillar of support whenever required.

2017

A test program was developed to evaluate the effectiveness of vacuum reflow processing on solder joint voiding and subsequent thermal cycling performance. Area array package test vehicles were assembled using conventional reflow processing and a solder paste that generated substantial void content in the solder joints. Half of the population of test vehicles then were re-processed (reflowed) using vacuum reflow. Transmission x-ray inspection showed a significant reduction in solder voiding after vacuum processing. The solder attachment reliability of the conventional and vacuum reflowed test vehicles was characterized and compared using two different accelerated thermal cycling profiles. The thermal cycling results are discussed in terms of the general impact of voiding on solder thermal fatigue reliability, results from the open literature, and the evolving industry standards for solder voiding. Recommendations are made for further work based on other void reduction methods and add...

2010

Voids in BGA/CSP package to substrate connections can cause issues with thermal management, drop shock resistance, and signal interference. Zero voids are always the best solution, but this is not always easy to achieve. Solder paste printing, reflow, alloy and flux chemistry all have significant influences on the amount of voiding one can expect in an assembly. This paper will discuss how print volume (stencil design), peak reflow temperature, paste flux chemistry and alloy selection affect the level of voiding to be expected when BGA/CSP packages are assembled in a lead free process. INTRODUCTION Voids in solder joints are considered one of the more detrimental defects in electronic assembly as area array devices have now evolved to a point where mass production of fine pitch devices with increasing functionality are common. The factors affecting void formation are complex and involve the interaction of many factors. In area array components such as BGA (Ball Grid Array), PBGA (Pl...

The increase in thermal failures associated with the operations of microelectronic devices at elevated temperature has accounted for some of their recent reliability concerns. The removal of heat with heat sink from chip level devices used in microelectronics assembly such as laptop computers is the key to achieving high reliability. Normally, when a heat sink is mounted on the chip level device, the surface roughness which exists at the interface is filled with air and it impacts heat transfer across the boundaries. Thermal interface materials (TIMs) are used to eliminate the interstitial air gaps from the interface by conforming to the topography of the surfaces in contact. In this paper, steady state thermal analysis built into finite element method was employed. The architecture and thermal conductivity of solder TIMs were varied to investigate their impact on thermal resistance of the TIM which in turn influences the thermal performance of the electronic package. The results obtained show that a solder thermal conductivity and bond line thickness less than 0.1 mm does not have a great impact on the thermal performance of the microelectronic device. In addition, a 75% and above TIM coverage area is required for optimum thermal performance. It is anticipated that the results will assist design engineers involved in setting standard for TIM architecture and thermal conductivity.

In this study, the detection and evaluation of defects at Pb-free BGA solder joints (SAC387, 95.5wt%Sn/ 3.8wt%Ag/ 0.7wt%Cu) in Printed Circuit Boards (PCB) placed under different thermal cycle conditions are investigated. By using digital radiography X-ray technique, the soldering defects in the packages including bridges, voids, ball missing, poor wetting, and tilted balls are identified. Subsequently, the thermal mechanical behaviours of the selected defective BGA packages are investigated by high temperature Moiré method. Based on the shear strain values obtained from Moiré tests, the fatigue life of defective and non-defective BGA packages subjected to thermal cycling tests is predicted and compared. It shows that various defect will have different influences on the thermal mechanical behaviours and reliability of a BGA package. The decrease in lifetime of defective packages depends on temperature and the defect classification. The experimental results achieved will provide valuable data for further optimization of Pb-free BGA design.