Academia.eduAcademia.edu

Outline

Title
Abstract
Introduction
Related Work
Conclusions
References
All Topics
Computer Science
Hardware and Architecture

Reversible Logic-Based Fault-Tolerant Nanocircuits in QCA

Profile image of Bibhash SenBibhash Sen

2013, ISRN Electronics

https://doi.org/10.1155/2013/850267
visibility

…

description

10 pages

link

1 file

Abstract

Parity-preserving reversible circuits are gaining importance for the development of fault-tolerant systems in nanotechnology. On the other hand, Quantum-dot Cellular Automata (QCA), a potential alternative to CMOS, promises efficient digital design at nanoscale. This work targets design of reversible ALU (arithmetic logic unit) in QCA (Quantum-dot Cellular Automata) framework. The design is based on the fault tolerant reversible adders (FTRA) introduced in this paper. The proposed fault tolerant adder is a parity-preserving gate, and QCA implementation of FTRA achieved 47.38% fault-free output in the presence of all possible single missing/additional cell defects. The proposed designs are verified and evaluated over the existing ALU designs and found to be more efficient in terms of design complexity and quantum cost.

References (18)

  1. R. Landauer, "Irreversibility and heat generation in the comput- ing process, " IBM Journal of Research and Development, vol. 5, no. 3, pp. 183-191, 1961.
  2. C. H. Bennett, "Logical reversibility of computation, " IBM Jour- nal of Research and Development, vol. 17, no. 6, pp. 525-532, 1973.
  3. C. S. Lent, P. D. Tougaw, W. Porod, and G. H. Bernstein, "Quantum cellular automata, " Nanotechnology, vol. 4, no. 1, pp. 49-57, 1993.
  4. Z. Guan, W. Li, W. Ding, Y. Hang, and L. Ni, "An arithmetic logic unit design based on reversible logic gates, " in Proceedings of the 13th IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PacRim '11), pp. 925-931, August 2011.
  5. M. Morrison and N. Ranganathan, "Design of a reversible ALU based on novel programmable reversible logic gate structures, " in Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI '11), pp. 126-131, Washington, DC, USA, July 2011.
  6. Y. Syamala and A. V. N. Tilak, "Reversible arithmetic logic unit, " in Proceedings of the 3rd International Conference on Electronics Computer Technology (ICECT '11), pp. 207-211, April 2011.
  7. J. W. Bruce, M. A. Thornton, L. Shivakumaraiah, P. S. Kokate, and X. Li, "Efficient adder circuits based on a conservative reversible logic gate, " in Proceedings of IEEE Symposium on VLSI, pp. 83-88, Washington, DC, USA, 2002.
  8. M. Haghparast and K. Navi, "A novel fault tolerant reversible gate for nanotechnology based systems, " American Journal of Applied Sciences, vol. 5, no. 5, pp. 519-523, 2008.
  9. Md. S. Islam, M. M. Rahman, Z. Begum, and M. Z. Hafiz, "Efficient approaches for designing fault tolerant reversible carry look-ahead and carry-skip adders, " MASAUM Journal of Basic and Applied Sciences, vol. 1, no. 3, pp. 354-360, 2009.
  10. S. K. Mitra and A. R. Chowdhury, "Minimum cost fault tolerant adder circuits in reversible logic synthesis, " in Proceedings of the 25th International Conference on VLSI Design (VLSID '12), pp. 334-339, January 2012.
  11. K. Walus, T. J. Dysart, G. A. Jullien, and R. A. Budiman, "QCADesigner: a rapid design and simulation tool for quan- tum-dot cellular automata, " IEEE Transactions on Nanotechnol- ogy, vol. 3, no. 1, pp. 26-31, 2004.
  12. T. Toffoli, "Reversible computing, " in Proceedings of the 7th Colloquium on Automata, Languages and Programming, pp. 632-644, Springer, London, UK, 1980.
  13. M. Perkowski, M. Lukac, P. Kerntopf et al., "A hierarchical approach to computer-aided design of quantum circuits, " in Proceedings of the 6th International Symposium on Representa- tions and Methodology of Future Computing Technology, pp. 201- 209, 2003.
  14. B. Parhami, "Fault-tolerant reversible circuits, " in Proceedings of the 40th Asilomar Conference on Signals, Systems, and Comput- ers (ACSSC '06), pp. 1726-1729, November 2006.
  15. X. Ma and F. Lombardi, "Fault tolerant schemes for QCA sys- tems, " in Proceedings of the 23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT '08), pp. 236-244, October 2008.
  16. M. B. Tahoori, J. Huang, M. Momenzadeh, and F. Lombardi, "Testing of quantum cellular automata, " IEEE Transactions on Nanotechnology, vol. 3, no. 4, pp. 432-442, 2004.
  17. M. Momenzadeh, M. Ottavi, and F. Lombardi, "Modeling QCA defects at molecular-level in combinational circuits, " in Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT '05), pp. 208-216, October 2005.
  18. M. Ottavi, L. Schiano, F. Lombardi, and D. Tougaw, "HDLQ: a HDL environment for QCA design, " Journal on Emerging Tech- nologies in Computing Systems, vol. 2, no. 4, pp. 243-261, 2006.

Related papers

A Novel Design and Evaluation of a Low Power Efficient Fault-Tolerant Reversible ALU Using QCA: Applications of Nanoelectronics
mary swarna latha gade

2021

Reversible logic based on Quantum-dot Cellular Automata (QCA) is the most requirement for achieving nano-scale architecture that promises significantly high device integration density, high-speed calculation, and low power consumption. The arithmetic logic unit (ALU) is the significant component of a processor for processing and computing. The primary objective of this work is to develop a multi-layer fault-tolerant arithmetic logic unit using reversible logic in QCA technology. Additionally, the reversible ALU has divided into arithmetic (RAU) and a logic unit (RLU). A reversible 2:1 MUX using the Fredkin gate has been implemented to select either the arithmetic or logical operations. Besides, to improve the efficiency of arithmetic operations, a novel QCA reversible full adder is implemented. To build the ALU, fault-tolerant reversible logic gates are used. The proposed reversible multilayer QCA ALU is designed to carry out eight arithmetic and sixteen logical operations with a mi...

View PDFchevron_right
Realization of a Novel Fault Tolerant Reversible Full Adder Circuit in Nanotechnology
Mohd Hafiz

The International Arab Journal of Information Technology, 2010

In parity preserving reversible circuit, the parity of the input vector must match the parity of the output vector. It renders a wide class of circuit faults readily detectable at the circuit's outputs. Thus reversible logic circuits that are parity preserving will be beneficial to the development of fault tolerant systems in nanotechnology. This paper presents an efficient realization of well known Toffoli gate using only two parity preserving reversible gates. The minimum number of garbage outputs and constant inputs required to synthesize a fault tolerant reversible full adder circuit has also been given. Finally, this paper presents a novel fault tolerant reversible full adder circuit and demonstrates its superiority with the existing counterparts.

View PDFchevron_right

Related topics

  • Computer Science
  • Logic Gate

    • Cited by

    Design of a fault-tolerant reversible control unit in molecular quantum-dot cellular automata
    golnaz bahadori

    International Journal of Quantum Information

    Quantum-dot cellular automata (QCA) is a promising emerging nanotechnology that has been attracting considerable attention due to its small feature size, ultra-low power consuming, and high clock frequency. Therefore, there have been many efforts to design computational units based on this technology. Despite these advantages of the QCA-based nanotechnologies, their implementation is susceptible to a high error rate. On the other hand, using the reversible computing leads to zero bit erasures and no energy dissipation. As the reversible computation does not lose information, the fault detection happens with a high probability. In this paper, first we propose a fault-tolerant control unit using reversible gates which improves on the previous design. The proposed design is then synthesized to the QCA technology and is simulated by the QCADesigner tool. Evaluation results indicate the performance of the proposed approach.

    View PDFchevron_right
    580 California St., Suite 400
    San Francisco, CA, 94104
    © 2025 Academia. All rights reserved