A new truncation algorithm of low hardware cost multiplier

Truncated multiplier is a good candidate for digital signal processing (DSP) applications including finite impulse response (FIR) and discrete cosine transform (DCT). Through truncated multiplier a significant reduction in Field Programmable Gate Array (FPGA) resources can be achieved. This paper presents for the first time a comparison of resource utilization of Spartan-3AN and Virtex-5 implementation of standard and truncated multipliers using Very High Speed Integrated Circuit Hardware Description Language (VHDL). The Virtex-5 FPGA shows significant improvement as compared to Spartan-3AN FPGA device. The Virtex-5 FPGA device shows better performance with a percentage ratio of number of occupied slices for standard to truncated multipliers is increased from 40% to 73.86% as compared to Spartan-3AN is decreased from 68.75% to 58.78%. Results show that the anomaly in Spartan-3AN FPGA device average connection and maximum pin delay have been efficiently reduced in Virtex-5 FPGA device.

Mahmoud A.M. Alshewimy, 2017

Abstract— New delay-efficient configurable multiplier based on Modified Booth’s Algorithm (MBA) and Wallace Tree (WT) structure for multiplying two m-bit operands - where m ranges from 8-bit to 128-bit – is introduced. WT structure has been used to reduce the number of sequential adding stages and speed improvements have been achieved. Modifying Booth’s multiplier architecture at a fundamental level is an advantageous concept that sets FPGA based multiplier models apart from rigidarchitecture conventional multipliers. In the context of this work, various multipliers, based on MBA and WT, have been developed with the smallest possible time delay. Comparisons have been made between the proposed multiplier implementations and those found in the literature. The comparative results show that the proposed multiplier introduces delay improvement reaches % 42.64.

Recent Approximate computing is a change in perspective in energy-effective frameworks plan and activity, in light of the possibility that we are upsetting PC frameworks effectiveness by requesting a lot of precision from them. Curiously, enormous number of utilization areas, like DSP, insights, and AI. Surmised figuring is appropriate for proficient information handling and mistake strong applications, for example, sign and picture preparing, PC vision, AI, information mining and so forth Inexact registering circuits are considered as a promising answer for lessen the force utilization in inserted information preparing. This paper proposes a FPGA execution for a rough multiplier dependent on specific partial part-based truncation multiplier circuits. The presentation of the proposed multiplier is assessed by contrasting the force utilization, the precision of calculation, and the time delay with those of a rough multiplier dependent on definite calculation introduced. The estimated configuration acquired energy effective mode with satisfactory precision. When contrasted with ordinary direct truncation proposed model fundamentally impacts the presentation. Thusly, this novel energy proficient adjusting based inexact multiplier design outflanked another cutthroat model.

This paper presents a comparative analysis of different multiplier architectures. The different multipliers architectures are array multiplier, a column bypass multiplier, row bypass multiplier and an array multiplier using Reversible Logic schemes. The multipliers are implemented on Spartan 2 FPGA. The architectures are compared in terms of critical path delay, power dissipation and area (resource usage in FPGA). The different multipliers are compared in terms of dynamic power consumption due to the scaling effects on leakage current. Each of these multipliers has its own trade-offs between power and delay. At last a novel multiplier is proposed, in which the number of layers is reduced to three, this will reduce the hardware resource usage and power consumption of design.

The programmable truncated Vedic multiplication is the method which uses Vedic multiplier and programmable truncation control bits and which reduces part of the area and power required by multipliers by only computing the most-significant bits of the product. The basic process of truncation includes physical reduction of the partial product matrix and a compensation for the reduced bits via different hardware compensation sub circuits. These results in fixed systems optimized for a given application at design time. A novel approach to truncation is proposed, where a full precision vedic multiplier is implemented, but the active section of the truncation is selected by truncation control bits dynamically at run-time. Such architecture brings together the power reduction benefits from truncated multipliers and the flexibility of reconfigurable and general purpose devices. Efficient implementation of such a multiplier is presented in a custom digital signal processor where the concept of software compensation is introduced and analyzed for different applications. Experimental results and power measurements are studied, including power measurements from both post-synthesis simulations and a fabricated IC implementation. This is the first system-level DSP core using a high speed Vedic truncated multiplier. Results demonstrate the effectiveness of the programmable truncated MAC (PTMAC) in achieving power reduction, with minimum impact on functionality for a number of applications. On comparison with the previous parallel multipliers Vedic should be much more fast and area should be reduced. Programmable truncated Vedic multiplier (PTVM) should be the basic part implemented for the arithmetic and PTMAC units.

There are mainly four series of Parallel Digital-Multipliers: Array, Vedic, Booth and Wallace series of multipliers. In this paper, a multiplier is proposed. This proposed multiplier has better performance than the other four types of series of multipliers. The proposed multiplier is actually a modified version of Wallace and Dadda multipliers. This paper presents a comparison of the proposed multiplier with these four types of series of multipliers. From each series, one multiplier which is the best among its series is selected for comparison by doing literature review of that series of multiplier. The comparison is in terms of delay, power and area. The selected multipliers with the proposed multiplier are implemented on front-end modeling using Verilog-HDL. For simulation, Modelsim is used and for synthesis and implementation Vivado is used. The target technology used for implementation is the FPGA, Z-board (xc7z020clg484-1).

International Journal of Engineering and Technology, 2012

High speed multiplication has always been a fundamental requirement of high performance processors and systems. With MOS scaling and technological advances there is a need for design and development of high speed data path operators such as adders and multipliers to perform signal processing operations at very high speed supporting higher data rates. In DSP applications, multiplication is one of the most utilized arithmetic operations as part of filters, convolves and transforms processors. Improving multipliers design directly benefits the high performance embedded processors used in consumer and industrial electronic products. Hence there is a need for design and development of high-speed architectures for N-bit multipliers supporting high speed and power. Here we review the architecture reported in the literature for multipliers and critical issues degrading the speed and power of these multiplier. Based on this review suitable modifications are suggested in the design for high speed and low power multipliers.

IJRET, 2013

As the scale of integration keeps growing, more and more sophisticated signal processing systems are being implemented on a VLSI chip. These signal processing applications not only demand great computation capacity but also consume considerable amounts of energy. While performance and area remain to be two major design goals, power consumption has become a critical concern in today’s VLSI system design. Multiplication is a fundamental operation in most arithmetic computing systems. Multipliers have large area, long latency and consume considerable power. Previous work on low-power multipliers focuses on low-level optimizations and has not considered well the arithmetic computation features and application-specific data characteristics. Binary multiplier is an integral part of the arithmetic logic unit (ALU) subsystem found in many processors. Booth's algorithm and others like Wallace-Tree suggest techniques for multiplying signed numbers that works equally well for both negative and positive multipliers. In this paper, we have used VHDL for describing and verifying a hardware design based on Booth's and some other efficient algorithms. Timing and correctness properties were verified. Instead of writing Test-Benches & Test-Cases we used Wave-Form Analyzer which can give a better understanding of Signals & variables and also proved a good choice for simulation of design

—This paper proposes a design method for an 8-bit multiplication with reduced delay time. Normally, two numeric data can be multiplied by repeated addition. In case of binary multiplication, combinational circuit can be designed using manual multiplication method which requires binary addition. Carry generated because of addition affects the speed of multiplication since the present addition depends on the value of previous carry. To overcome this problem, addition with the help of multiplexer is introduced and the result is an increased speed in multiplication. Even though the proposed design is mainly for FPGA implementation, it can also be implemented in ASIC as the logical delay is reduced when compared the result in Xilinx device.

2019

This paper suggests a low power fixed-width multiplier using a reduced precision redundancy unit (RPR) for VLSI signal processing applications. RPR consists of a reduced precision module and a full precision module. The result of the reduced precision is considered as the correct output when the source output computes falsely. The proposed RPR fixed-width multiplier can satisfy the demand for accuracy, area efficiency, processing speed, and low power consumption. The precision of the proposed multiplier will be enhanced by the RPR logic. The compensation bias consists of probability and statistics. To avoid the truncation error many types of rounding methods are employed. The proposed RPR fixed-width multiplier is installed in the FIR filter design for various signal processing applications. The detailed analysis of the suggested multiplier gives 30% power reduction and 46.54% area reduction as compared with the different techniques.