Glen Offord
580 California St., Suite 400
San Francisco, CA, 94104
A high speed, low power PRML read channel device
1995, IEEE Transactions on Magnetics
https://doi.org/10.1109/20.364805
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Abstract
A complete read channel device using PR-IV signalling and maximum likelihood detection is described. Descriptions, simulated performance and measured results of the digital adaptive feedback loops (AGC, FIR tap weights, DFE tap weights, frequency and phase) in the read channel are presented. Analog FIR filter and flash A/D converter performance is presented. The weighted averaging servo demodulation technique used in the device is described and compared to integration. This monolithic CMOS device consumes less than 0.75 W when reading at 85 Mbps, and occupies a step-and-repeat area of 24.6 mm2. While PRML (Partial Response, Maximum Likelihood) read channels have existed [l] for many years, monolithic implementations of the technique [2-51 have appeared only recently, and have suffered from high read mode power consumption, low maximum data rates, and high chip area. A large portion of these problems can be traced to the use of digital filtering, in particular, to the use of digital FIR equalization, which, at current linewidths, and at the required speeds, is a very power and area intensive technique; in order to avoid this expense, an inadequate number of FIR taps has sometimes been used [2], but this is not an appealing solution. In addition to the area and power benefits, it will be shown that the required resolution of the AID converter can be reduced when the FIR filter is analog. As track spacing in rotating media reduces each year, it should be obvious that a high-quality read channel is useless if it is coupled to a lower quality servo demodulator. While integrating servo demodulation is becoming more common, it has a complexity disadvantage when compared to peak detection. Weighted averaging demodulation, which will be presented here, is only slightly more complicated than peak detection, and can produce performance superior to integrating demodulation. As Viterbi detection has been well described elsewhere [ 1,6-71, it will not be discussed here. This paper focuses on the read channel and the servo demodulation; the ENDEC, write precompensation, clock synthesizer, pulse position detector, serial interface, power control, and testability circuitry will also not be discussed here.
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