Palani Design Of FFT Using ALU For Efficient OFDM Systems

Journal of Intelligent & Fuzzy Systems, 2017

In multi carrier OFDM systems parameters like speed, throughput and hardware area can be improved by using efficient Fast Fourier Transform approach. In this paper an area efficient and high speed 32 bit floating point FFT processor for OFDM using Vedic multiplication process is presented. Proposed FFT processor is based on memory based architecture and utilizing Urdhavatiraykbhyam sutra for Vedic multiplication. As the number of inbuilt multipliers available in FPGAs are limited, hence external multiplication module are required in the multicarrier OFDM systems, in order to reduce the complexity of FPGA implementation. By the use of Vedic multiplication process in FFT of OFDM high throughput with smaller area can be achieved. Simulation results explain that the proposed scheme is having high speed and throughput.

In several wired and wireless applications high-speed performance is required, which is only possible by using conventional multi-carrier transmission techniques, but this will results in the lowering of spectrum efficiency. So, in such applications the principle of Orthogonal Frequency Division Multiplexing (OFDM) is used. This paper gives the details of the design, development and performance analysis of 8-point FFT algorithms to be used in OFDM systems based on the IEEE 802.11a standard for WLAN. Generally, the inverse Fast Fourier Transform (IFFT) and Fast Fourier Transform (FFT) operations are used as the modulation and demodulation in the OFDM systems, and the sizes of FFT/IFFT are varied in various applications of OFDM systems. Actually, in the complete architecture of OFDM system, all the mathematical manipulations take place in IFFT & FFT blocks while remaining blocks convert the data from one format to another format. VHDL programming language is used to develop the design and synthesized on Virtex-5 FPGA in Xilinx 14.2 software and Modelsim 10.1 is used for functional simulation.

2011 International Conference on Multimedia Computing and Systems, 2011

The Fast Fourier Transform (FFT) and its inverse transform (IFFT) processor are key components in many communication systems. An optimized implementation of the 8point FFT processor with radix-2 algorithm in R2MDC architecture is presented in this paper. The butterfly-Processing Element (PE) used in the 8-FFT processor reduces the multiplicative complexity by using a real constant multiplication in one method and eliminates the multiplicative complexity by using add and shift operations in other proposed method. The pipeline architecture R2MDC has been implemented with the 8point module and simulation results show that this module significantly achieves a better performance with lower resource usage.

Fourier Transform - Signal Processing, 2012

Orthogonal Frequency Division Multiplexing (OFDM) could be tracked to 1950's, but it had become very popular at these days, allowing high speeds at wireless communications. OFDM could be considered either a modulation or multiplexing technique, and its hierarchy corresponds to the physical and medium access layer.

International Journal of Engineering Sciences & Research Technology, 2013

Orthogonal Frequency Division Multiplexing (OFDM) is a multi-carrier modulation technique which divides the available spectrum into many carriers. OFDM uses the spectrum efficiently compared to FDMA. With the rapid growth of digital wireless communication in recent years, the need for high-speed mobile data transmission has increased. FPGAs have become key components in the implementation of high performance DSP systems.

OFDM technology promises to be a key technique for achieving the high data capacity and spectral efficiency requirements for wireless communication systems in future. Fast Fourier transform (FFT) processing is one of the key procedures in popular orthogonal frequency division multiplexing (OFDM) communication systems. A parallel and pipelined Fast Fourier Transform (FFT) processor for use in the Orthogonal Frequency division Multiplexer (OFDM). Unlike being stored in the ROM, the twiddle factors in our pipelined FFT processor can be accessed directly. The radix 4 FFT is proposed. Finally, the pipelined 64-point FFT processor can be completely implemented using Xilinx 13.2 software.

Low power consumption has become apparent need in the area of VLSI digital signal processing. This gives rise to the need of minimization of silicon area which can be done by folding algorithm. As silicon area decreases power consumption of a circuit decreases. Folding transformation is a technique which reduces silicon chip area by combining various arithmetic operations into one operation by time scheduling technique. It is applied on iterative with appropriate folding set. This paper presents an approach to design fast Fourier transform (FFT) architectures using folding transformation. Proposed work is focused on design of efficient VLSI architecture for FFT using radix-3 algorithm which aims at reducing mainly area which results in reduction of power consumption and hardware complexity. A proper procedure for designing FFT architectures using folding transformation and register minimization techniques is projected. Results show that numbers of adders are reduced by 37.5 % and multipliers by 33.33% without changing characteristics of FFT algorithms.

2001

Abstmct--In the paper, we propose an efficient FFT (Fast Fourier Transform) algorithm for OFDM (Orthogonal Frequency Division Multiplexing) modulation, named by "radix-42". This algorithm based on radix-4 butterfly operator reduces the number of non-trivial multiplications as like racuX-Z3 FFT algorithm, and it ha^ twice processing rate as radix-z3 FFT algorithm. With 64 -point and pipeline architecture, proposed radix42 algorithm reduces the number of non-trivial multiplications to the ratio of 3 to 2 compared with radix4 algorithm, and it has twice procesSing rate as radix-23 algorithm.

IJSRD, 2013

In the last few years wireless communications have experienced a fast growth due to the high mobility that they allow. However, wireless channels have some disadvantages like multipath fading that make them difficult to deal with. A modulation that efficiently deals with selective fading channels is OFDM. There are a large number of FFT algorithms and architectures in the signal processing literature. Therefore, the state of art algorithms and architectures should be analyzed and compared. Based on different algorithms and architectures, different power consumptions, area and speed of the processor will be achieved. So their ASIC suitability should be analyzed and the effort should be focused on the choosing algorithms and architectures and optimization. In this paper FFT Processor with Pipelined Architecture and CORDIC based ROM-free twiddle factor generator is proposed. The proposed algorithm and architecture should be validated by MATLAB simulation before implementation. After that, it is implemented on DSP Processor kit with Code Composer Studio. The synthesis results will be compared with other published FFT processor results.