The AM3Associative Processor

2006

Abstract Associative processors are single-instruction multiple-data-based architectures that provide huge parallelism which can be very useful for processing video in real time. This paper describes architectural requirements for video and shows that associative processors are ideally suited for applications involving video. Some routines like discrete cosine transforms (DCTs) lack required parallelism and their implementation becomes critical for the overall performance of the processor for video.

The modern computer systems that are in use nowadays are mostly processor-dominant, which means that their memory is treated as a slave element that has one major task-to serve execution units data requirements. This organization is based on the classical Von Neumann's computer model, proposed seven decades ago in the 1950 ties. This model suffers from a substantial processor-memory bottleneck, because of the huge disparity between the processor and memory working speeds. In order to solve this problem, in this paper we propose a novel architecture and organization of processors and computers that attempts to provide stronger match between the processing and memory elements in the system. The proposed model utilizes a memory-centric architecture, wherein the execution hardware is added to the memory code blocks, allowing them to perform instructions scheduling and execution, management of data requests and responses, and direct communication with the data memory blocks without using registers. This organization allows concurrent execution of all threads, processes or program segments that fit in the memory at a given time. Therefore, in this paper we describe several possibilities for organizing the proposed memory-centric system with multiple data and logicmemory merged blocks, by utilizing a high-speed interconnection switching network.

A motionless head 2-D parallel readout system for optical disks is prcsented. iLS unique features are discussed and it is compared to various parallel access optical storage media. The motionless-head parallel read-out system for optical disks is shown to meet current and near-term future requirements for high performance secondary storage. In order to select a memory architecture compatible with the motionless-head disk, inner-product and outer-product associative memory algorithms are compared in termsof their storage requirements, search times, system complexities, and fault tolerance. Based on this comparison, the page serial, bit-parallel inner-product method is shown to be well suited to implementation with parallel readout optical disk, and opto-electronic XNOR gate arrays, using for instance the Si/PLZT technology. Finally, the associative memory system design is presented. 14. SUBJECT TERMS IS NUMBER OF PAGES 60 Memory, Associative Memory, Optical Disks is PPiCE CODE 17. SECURITY CLASSIFICATION 18, SECURITY CLASSIFICATION 19. SECURITY CLASSIFICATION 20. UMITATION OF ABS1 RAC I

IEEE Micro, 2002

Computer, 2000

SIMD processing with large associative memories can support robust performance in speech applications. The IXM2 with 73 transputers has outclocked a Cray in some tasks.