Raimondo Luzzi
580 California St., Suite 400
San Francisco, CA, 94104
Supplemental cryptographic hardware for smart cards
2001, IEEE Micro
https://doi.org/10.1109/40.977755
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Abstract
This industry wide recognition expresses an essential fact. The specific properties of smart cards, compared with all other types of cards, are determined by a microcontroller integrated in a card, which controls, initiates, and monitors all activities. Smart card microcomputer architecture Most smart card microcomputer chips adopt a conventional von Neumann architecture, as Figure 1 shows. 2 Microcontroller The heart of a microprocessor card is a CPU surrounded by four functional blocks: ROM, Eeprom, RAM, and an I/O port. The card also has special circuits for security and power control. The ROM contains the chip operating system (or mask) which is burned in during fabrication. The ROM is efficient in terms of space and power requirements. The Eeprom nonvolatile memory is a costly component that takes up to 50 percent of the chip area. Data and program code can be written, usually by the smart card manufacturer, to and read from the Eeprom under the control of operating system. Flash memory, which is more efficient than Eeprom in terms of writing time, is also becoming common in smart cards. The RAM is the processor's working memory. It is volatile memory and small-typically up to 512 bytes. Within the card, data are passed through a bus under the security logic's control. Microcomputer memory partitioning and the logic that governs access to the partition are central design elements for smart card security. Cards have a single I/O interface, which takes various forms. Usually, it is a serial I/O interface consisting of a single register, through which the card transfers data. The vast majority of smart card microprocessors use an asynchronous byte-oriented protocol (T=0). The ISO/IEC 7816-3 standard (http://www.iso.ch) specifies this protocol,
References (10)
- W. Rankle and W. Effing, Smart Card Handbook, 2nd ed., John Wiley & Sons, New York, 2000.
- M. Hendry, Smart Card Security and Applications, Artech House, Boston, 1997.
- P. Kocher, J. Jaffe, and B. Jun, "Differential Power Analysis," Advances in Cryptology (Crypto 99), M. Wiener, ed., Lecture Notes in Computer Science 1666, Springer-Verlag, Heidelberg, Germany, 1999, pp. 388-397.
- The Intel Random Number Generator, technical report, Intel, 1999.
- C.S. Petrie and J.A. Connelly, "A Noise- Based IC Random Number Generator for Applications in Cryptography," IEEE Trans. Circuits and Systems I, vol. 47, no. 5, May 2000, pp. 615-621.
- V. Bagini and M. Bucci, "Design of Reliable True Random Number Generator for Cryptographic Applications," Cryptographic Hardware and Embedded Systems (CHES 99), Lecture Notes in Computer Science 1717, Springer-Verlag, Heidelberg, Germany, 1999, pp. 204-218.
- R. Luzzi, "System Architecture and Specification Definition: RNG1," Report Electronic Eng. Dept., Univ. Rome, La Sapienza, Dec. 2000.
- J. Daemen and V. Rijmen, "The Rijndael Block Cipher: AES Proposal," Proc. 1st AES Candidate Conf., 1998; http://www.esat. kuleuven.ac.be/~rijmen/rijndael.
- M. Bean et al., "Hardware Performance Simulations of Round 2 Advanced Encryption Standard Algorithms;" http://csrc.nist.gov/encryption/aes/round2/N SA-AESfinalreport.pdf (current Nov. 2001).
- H. Kuo and I. Verbauwhede, "Architectural Optimization for a 1.82-Gbits/sec VLSI Imple- mentation of the AES Rijndael Algorithm," Cryptographic Hardware and Embedded Sys-