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Computer Science
Embedded Systems

Implementation of PRINCE Algorithm in FPGA

Profile image of Baraa H TareqBaraa H TareqProfile image of Yasir A AbassYasir A AbassProfile image of Mohd E RusliMohd E RusliProfile image of Razali JidinRazali Jidin

Abstract

This paper presents a hardware implementation of the PRINCE block cipher in Field Programmable Gate Array (FPGA). In many security applications, the software implementations of cryptographic algorithms are slow and inefficient. In order to solve the problems, a new FPGA architecture was proposed to speed up the performance and flexibility of PRINCE algorithm. The concurrent computing design allows an encryption block data of 64 bits within one clock cycle, reducing the hardware area and producing a high throughput and low latency. It also showed high speed processing and consumed low power. To do this, firstly, the encryption, decryption and key schedule are all implemented with small hardware resources, Next, an efficient hardware architectural model for PRINCE algorithms was developed using very high speed integrated circuit hardware description language (VHDL). Finally, the VHDL design for PRINCE algorithm was synthesized in FPGA boards. Two FPGA boards were used in this study, which are Virtex-4 and Virtex-6. The results show a throughput of 2.03 Gbps and efficiency of 2.126 Mbps/slice for Virtex-4, whereas a throughput of 4.18 Gbps and efficiency of 8.681 Mbps/slice for Virtex-6.

FAQs

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What advantages does PRINCE offer for low area FPGA implementations?add

The study reveals that PRINCE successfully achieves encryption within one clock cycle, enabling low latency. Compared to other algorithms, it demonstrates a significant area efficiency of 8.681 Mbps/slice on Virtex-6.

How does PRINCE's throughput compare across different FPGA boards?add

PRINCE achieved a throughput of 2.03 Gbps on Virtex-4 and 4.18 Gbps on Virtex-6. This highlights a substantial performance increase in newer FPGA architectures.

What key design choices contribute to PRINCE's low power consumption?add

The hardware model for PRINCE employs a concurrent design with no block RAM, facilitating low power usage at 0.165W for Virtex-4 and 2.875W for Virtex-6. This design choice minimizes power requirements while maintaining high throughput.

How does the S-box layer impact the overall resource usage in PRINCE implementations?add

The S-box layer is identified as the most resource-intensive component of the PRINCE design. By optimizing this layer, the implementation achieves significant reductions in slice usage compared to traditional designs.

What role does the key schedule play in PRINCE's encryption efficiency?add

The key schedule in PRINCE was designed to minimize overhead by utilizing wiring for shift operations. This optimization reduces the area requirement to only one slice in FPGA boards.

Figures (4)
Fig. 2. The data flow of the PRINCE encryption unit. Figure 3 shows the interface of the block cipher in our design. The design involves three ports; two ports for input the 64-bit plaintext and the 128-bit key and the third interface port is representing the 64-bit ciphertext. Since the total number of the pins that was used as input/output is 256, therefore we decided to select a large FPGA board, such as Virtex 4 or Virtex 6 because these boards have a big number of input/output pins as well as a large number of logic resources.
Fig. 2. The data flow of the PRINCE encryption unit. Figure 3 shows the interface of the block cipher in our design. The design involves three ports; two ports for input the 64-bit plaintext and the 128-bit key and the third interface port is representing the 64-bit ciphertext. Since the total number of the pins that was used as input/output is 256, therefore we decided to select a large FPGA board, such as Virtex 4 or Virtex 6 because these boards have a big number of input/output pins as well as a large number of logic resources.
Fig. 3. The Top module interface of the PRINCE.
Fig. 3. The Top module interface of the PRINCE.
Fig. 6. The Simulation of PRINCE Core.
Fig. 6. The Simulation of PRINCE Core.

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