Research directions and challenges in nanoelectronics

ECS Transactions, 2022

Since the last six decades, technology node has grown smaller from micrometer to nanometer dimensions. In continuation of Moore's Law, the research is going on for device/ supply voltage shrinking to go beyond 22 nm CMOS technology node. However, many physical and quantum challenges appear at a smaller scale, which causes shrinking beyond 22nm critical and needs innovative materials and devices for scaling in the nanometer regime. Incorporating nanoengineered materials to realize research achievements has shown timely development with significant influence in electronic industries. These new materials and devices hold promise as potential device candidates to be integrated onto the silicon platform to enhance semiconductor industry growth and extend Moore's Law. Here we address stateof-the-art research trends in nanomaterials and nanodevices for future technology node and discuss associated challenges.

Nanotechnology, 2010

2004

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Nanotechnology, …, 2009

We provide an outlook of some important state variables for emerging nanoelectronic devices. State variables are physical representations of information used to perform information processing via memory and logic functionality. Advances in material science, emerging nanodevices, nanostructures, and architectures have provided hope that alternative state variables based on new mechanisms, nanomaterials, and nanodevices may indeed be plausible. We review and analyze the computational advantages that alternate state variables may possibly attain with respect to maximizing computational performance via minimum energy dissipation, maximum operating switching speed, and maximum device density.

Microelectronic …, 2005

Denoting with ÔnanodeviceÕ any device with size in one dimension at least in the nanometre length scale (NLS), the basic constituent of integrated circuits (ICs), the metal-oxide-semiconductor (MOS) field-effect transistor (FET), is by several years a nanodevice. In fact, the thickness of the SiO 2 gate dielectric is around 3 nm for logics or 5 nm for nonvolatile memories. However, since the factors limiting the IC integration are horizontal sizes, in electronics one speaks of nanodevice when its size in one horizontal dimension at least is in the NLS. The definition of features in the NLS is impossible via optical lithography, but can be done using electron-or ion-beam lithography. These techniques, however, are very expensive and still in their fancy, at least for what concerns their exploitation in the industry practice. Geometries in the NLS can however be produced with relative ease by the spacer patterning technique, i.e., transforming vertical features (like film thickness) in the vicinity of a step of a sacrificial layer into horizontal features. The ultimate length producible in this way is controlled by: the steepness of the step defining the sacrificial layer; the uniformity of the deposited or grown films; and the anisotropy of its etching. While useful for the preparation of a few devices with special needs, the above trick does not allow by itself the development of a nanotechnology, where each layer useful for defining the FET should be in the NLS and aligned on the underlying geometries with tolerances in the NLS. Setting up such a nanotechnology is a major problem which will involve the IC industry in the post-Roadmap era. Irrespective of the detailed structure of the basic constituents of nanoICs (molecules, supramolecular structures, clusters, etc.), any nanoIC can hardly be prepared without the ability to produce arrays of conductive strips with pitch in the NLS. This work is devoted to describe a scheme (essentially based on the existing microelectronic technology) for their production without the use of electron-or ion-beam lithography and used as host of molecular devices.

Electronic Materials: Science & Technology, 2004

In this paper we discuss the foundation technologies that have kindled and are reinforcing the shift of microelectronics to nanoelectronics. Nano electronics is the science which deals with the electronic components manufactured and engineered at a molecular scale. Today's electronics world is dominated by the micro-level silicon based technology which follows the famous Moore's law. Further miniaturization is hindered by certain physical, thermal and manufacturing problems. The paper discusses about combating these problems with various nano materials, new device architectures and using them onto the CMOS circuitry. Carbon nanotube (CNT), graphene Nano ribbon (GNR), Semiconducting Nanowire (S-NW) and molecular electronic devices are the potential materials which can modify the pre-existing silicon based technology. Miniaturization of FETs to the nano-level is accompanied by leakage current and power losses, fully depleted tri-gate transistors provide a promising solution. Studies have proved that electrical, thermal, mechanical, physical and chemical properties of nano-materials are superior to silicon. Graphene shows excellent electrical and thermal properties, major research being pursued to exploit these properties by employing graphene in electronics world. This nano-circuitry can find its use in digital circuits, display applications, TFTs, printed electronics, high precision sensors, radio frequency (RF) signal processing and flexible electronics. The paper also discusses various limitations in manufacturing of these nanomaterials at a large scale to launch them in the commercial market. There are certain demerits of the aforementioned nano-materials which stand as challenges to be tackled. The major obstacles are fabrication of such nano-sized FETs, nano-wires and placing them onto the CMOS circuitry with ultra-high precision, high values of yield and a production rate so as to meet the unprecedented demand of these components in the market.

The technical and economic growth of the twentieth century was marked by evolution of electronic devices and gadgets. The day-to-day lifestyle has been significantly affected by the advancement in communication systems, information systems and consumer electronics. The lifeline of progress has been the invention of the transistor and its dynamic up-gradation. Discovery of fabricating Integrated Circuits (IC’s) revolutionized the concept of electronic circuits. With advent of time the size of components decreased, which led to increase in component density. This trend of decreasing device size and denser integrated circuits is being limited by the current lithography techniques. Non-uniformity of doping, quantum mechanical tunneling of electrons from source to drain and leakage of electrons through gate oxide limit scaling down of devices. Heat dissipation and capacitive coupling between circuit components becomes significant with decreasing size of the components. Along with the intrinsic technical limitations, downscaling of devices to nanometer sizes leads to a change in the physical mechanisms controlling the charge propagation. To deal with this constraint, the search is on to look around for alternative materials for electronic device application and new methods for electronic device fabrication. Such material is comprised of organic molecules, proteins, carbon materials, DNA and the list is endless which can be grown in the laboratory. Many molecules show interesting electronic properties, which make them probable candidates for electronic device applications. The challenge is to interpret their electronic properties at nanoscale so as to exploit them for use in new generation electronic devices. Need to trim downsize and have a higher component density have ushered us into an era of nanoelectronics.

IEEE Journal of the Electron Devices Society, 2021

of America. He serves as a member of the Distinguished Lecturer program of the Electron Devices Society. He has been a member of advisory and technical committees in several international and national conferences. Arturo Escobosa received the Ph.D. degree from RWTH, Aachen, Germany. He is a full-time Professor with the Electrical Engineering Department, Cinvestav, Mexico, where he has been a member of the Solid-State Electronics Section. His research activity includes the fields of III-V semiconducting compounds, optoelectronic devices, MOCVD growth, optical characterization of electronic materials, and X-ray diffraction techniques. He has volunteered at the Electron Devices Society, as a member of technical committees. He was an Elected Member of the EDS Board of Governors from 2010 to 2016. Since 2018, he has been the Region Chair of EDS Region and Chapters Committee.

NATURE NANOTECHNOLOGY | VOL 9 | OCTOBER 2014 | www.nature.com/naturenanotechnology 1 T he shrinking of the geometrical dimensions of planar devices 1 , plus the introduction of additional performance boosters such as strain, high-k gate dielectrics (where k is relative dielectric constant) and metal gates, have been successful approaches for improving transistor performance in the past 60 years (ref. 2). Furthermore, the semiconductor industry has taken advantage of the third dimension by putting into production the tri-gate transistor 3 illustrated in for the 22-nm node 4 . Together with planar ultrathin body (UTB) technology 5 , three-dimensional (3D) devices represent an alternative to bulk planar technology, which may not provide significant performance improvements below the 22-nm node. Indeed, in bulk planar devices, good electrostatic control of the channel by the gate voltage requires prohibitively thin gate oxides, which leads to increased leakage, to very high substrate doping and eventually to charge carrier mobility (μ) degradation. In the case of tri-gate and UTB transistors, however, issues related to leakage and doping levels are mitigated.