Approximate Computing-Based Processing of MEA Signals on FPGA

TELKOMNIKA Telecommunication Computing Electronics and Control, 2019

This paper investigates about the possibility to reduce power consumption in Neural Network using approximated computing techniques. Authors compare a traditional fixed-point neuron with an approximated neuron composed of approximated multipliers and adder. Experiments show that in the proposed case of study (a wine classifier) the approximated neuron allows to save up to the 43% of the area, a power consumption saving of 35% and an improvement in the maximum clock frequency of 20%.

2005

A real-time, large scale, leaky-integrate-and-fire neural network processor realized using FPGA is presented. This has been designed, as part of a collaborative project, to investigate and implement biologically plausible models of the rodent vibrissae based somatosensory system to control a robot. An emphasis has been made on hard real-time performance of the processor, as it is to be used as part of a feedback control system. This has led to a revision of some of the established modelling protocols used in other hardware spiking neural network processors. The underlying neuron model has the ability to model synaptic noise and inter-neural propagation delays to provide a greater degree of biological plausibility. The processor has been demonstrated modelling real neural circuitry in real-time, independent of the underlying neural network activity.

Solid State Phenomena, 2013

This paper presents a new distance calculation circuit (DCC) that in artificial neural networks is used to calculate distances between vectors of signals. The proposed circuit is a digital, fully parallel and asynchronous solution. The complexity of the circuit strongly depends on the type of the distance measure. Considering two popular measures i.e. the Euclidean (L2) and the Manhattan (L1) one, it is shown that in the L2 case the number of transistors is even ten times larger than in the L1 case. Investigations carried out on the system level show that the L1 measure is a good estimate of the L2 one. For the L1 measure, for an example case of 4 inputs, for 10 bits of resolution of the signals, the number of transistors is equal to c. 2500. As transistors of minimum sizes can be used, the chip area of a single DCC, if realized in the CMOS 180 nm technology, is less than 0.015 mm 2 .

Lecture Notes in Computer Science, 2005

The current growth of neuron technology is reflected by the increasing focus on this research area within the European research community. One topic is the implementation of neural networks (NNs) onto silicon. FPGAs provide an excellent platform for such implementations. The development of NNs has led to multiple abstractions for various generations. The different demands that each generation pose, present different design challenges. This has left ambiguous decisions for the neuroengineer into what model to implement. The authors have undertaken an investigation into four commonly selected neuron models, two classical models and two formal spike models. A software classification problem is combined with hardware resource requirements for FPGAs, implemented utilising a novel design flow. This provides an overall comparative analysis to be made and identification of the most suitable model to implement on an FPGA.

Neural Information Processing, …, 2002

As FPGAs have increasingly become denser and faster, they are being utilized for many applications, including the implementation of neural networks. Ideally, FPGA implementations, being directly in hardware and having parallelism, will have performance advantages over software on conventional machines. But there is a great deal to be done to make the most of FPGAs and to prove their worth in implementing neural networks, especially in view of past failures in the implementation of neurocomputers. This paper looks at some of the relevant issues.

Frontiers in Neuroscience, 2017

In the last years, the idea to dynamically interface biological neurons with artificial ones has become more and more urgent. The reason is essentially due to the design of innovative neuroprostheses where biological cell assemblies of the brain can be substituted by artificial ones. For closed-loop experiments with biological neuronal networks interfaced with in silico modeled networks, several technological challenges need to be faced, from the low-level interfacing between the living tissue and the computational model to the implementation of the latter in a suitable form for real-time processing. Field programmable gate arrays (FPGAs) can improve flexibility when simple neuronal models are required, obtaining good accuracy, real-time performance, and the possibility to create a hybrid system without any custom hardware, just programming the hardware to achieve the required functionality. In this paper, this possibility is explored presenting a modular and efficient FPGA design of an in silico spiking neural network exploiting the Izhikevich model. The proposed system, prototypically implemented on a Xilinx Virtex 6 device, is able to simulate a fully connected network counting up to 1,440 neurons, in real-time, at a sampling rate of 10 kHz, which is reasonable for small to medium scale extra-cellular closed-loop experiments.

IEEE Micro, 2000

This paper describes an implementation method of a simple neural architecture using FPGAs (Field Programmable Gate Array). For a hardware implementation of the architecture, the FPGA can exploit the parallelism potential of neural networks. By implementing all the concurrent tasks that can be executed simultaneously, the processing time can be reduced to a significant degree. Network modelling is developed from the model of a single neuron whose effectiveness of implementation plays a vital role on the performance of the network. This work also includes a description of the technique used to integrate a sigmoid activation function and its influence on the FPGA memory consumption which we try to optimize. A simple example of validation of this implementation is designed to compare the different results found in practice and simulation.

Frontiers in Neuroscience, 2019

Neurological diseases can be studied by performing bio-hybrid experiments using a real-time biomimetic Spiking Neural Network (SNN) platform. The Hodgkin-Huxley model offers a set of equations including biophysical parameters which can serve as a base to represent different classes of neurons and affected cells. Also, connecting the artificial neurons to the biological cells would allow us to understand the effect of the SNN stimulation using different parameters on nerve cells. Thus, designing a real-time SNN could useful for the study of simulations of some part of the brain. Here, we present a different approach to optimize the Hodgkin-Huxley equations adapted for Field Programmable Gate Array (FPGA) implementation. The equations of the conductance have been unified to allow the use of same functions with different parameters for all ionic channels. The low resources and high-speed implementation also include features, such as synaptic noise using the Ornstein-Uhlenbeck process and different synapse receptors including AMPA, GABAa, GABAb, and NMDA receptors. The platform allows real-time modification of the neuron parameters and can output different cortical neuron families like Fast Spiking (FS), Regular Spiking (RS), Intrinsically Bursting (IB), and Low Threshold Spiking (LTS) neurons using a Digital to Analog Converter (DAC). Gaussian distribution of the synaptic noise highlights similarities with the biological noise. Also, cross-correlation between the implementation and the model shows strong correlations, and bifurcation analysis reproduces similar behavior compared to the original Hodgkin-Huxley model. The implementation of one core of calculation uses 3% of resources of the FPGA and computes in real-time 500 neurons with 25,000 synapses and synaptic noise which can be scaled up to 15,000 using all resources. This is the first step toward neuromorphic system which can be used for the simulation of bio-hybridization and for the study of neurological disorders or the advanced research on neuroprosthesis to regain lost function.

This paper describes a generalized technique for designing, simulating and implementing an Artificial Neural Network (ANN) using Field Programmable Gate Array (FPGA). For a hardware implementation of the network, FPGA can exploit the parallelism potential of neural networks. By implementing all the concurrent tasks that can be executed simultaneously, the processing time can be reduced to a significant degree. Network modeling is developed from the model of a single neuron whose effectiveness of implementation plays an important role on the performance of the network, especially in terms of number of response cycles. This work also includes a description of the method used to integrate a hyperbolic tangent sigmoid (Tansig) activation function and its influence on FPGA memory consumption which we try to optimize. Two examples of function approximation are implemented to validate the different results found in practice and simulation. 1 INTRODUCTION Applications of neural networks cover a wide range of problems involving complex nonlinear relationships where traditional solutions are not valid. The reason for this diversity is justified through the benefits of this type of architecture. Indeed, neural networks offer simplicity of implementation and good adaptation with the parametric and environment variations. In addition, they have a parallel processing structure and an ability to learn through examples [1]. ANNs can be implemented easily in software applications since this method does not require detailed knowledge about the inner workings of the various network elements. However, a disadvantage in real-time applications of software-based ANNs is slower execution compared with other hardware-based ANNs [2]. FPGAs are reconfigurable and programmable devices that give a great flexibility in the development of many electronic circuits which make them suitable for hardware implementation of neural networks [3]. One of the important challenges in this work is to design a neuron model, using serial processing input mode, which is capable to offer a high speed response performance without deteriorating the memory usage. The results of the synthesis are compared to other results in related works. The comparison is done in terms of time and memory with the same serial processing mode [3], partial parallel processing [4, 5] and full parallel processing [5]. This paper is organized as follows. In Section 2, we introduce the artificial model of the neuron describing the principal function of each part, the coding method to represent the