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Title
Abstract
Figures
Introduction
Simt Deadlock Static Analysis
Implementation and Methodology
Related Work
Conclusion
References
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Computer Science
Distributed Systems

MIMD synchronization on SIMT architectures

Profile image of ahmed eltantawyahmed eltantawy

2016, 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

https://doi.org/10.1109/MICRO.2016.7783714
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14 pages

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Abstract

In the single-instruction multiple-threads (SIMT) execution model, small groups of scalar threads operate in lockstep. Within each group, current SIMT hardware implementations serialize the execution of threads that follow different paths, and to ensure efficiency, revert to lockstep execution as soon as possible. These constraints must be considered when adapting algorithms that employ synchronization. A deadlockfree program on a multiple-instruction multiple-data (MIMD) architecture may deadlock on a SIMT machine. To avoid this, programmers need to restructure control flow with SIMT scheduling constraints in mind. This requires programmers to be familiar with the underlying SIMT hardware. In this paper, we propose a static analysis technique that detects SIMT deadlocks by inspecting the application control flow graph (CFG). We further propose a CFG transformation that avoids SIMT deadlocks when synchronization is local to a function. Both the analysis and the transformation algorithms are implemented as LLVM compiler passes. Finally, we propose an adaptive hardware reconvergence mechanism that supports MIMD synchronization without changing the application CFG, but which can leverage our compiler analysis to gain efficiency. The static detection has a false detection rate of only 4%-5%. The automated transformation has an average performance overhead of 8.2%-10.9% compared to manual transformation. Our hardware approach performs on par with the compiler transformation, however, it avoids synchronization scope limitations, static instruction and register overheads, and debuggability challenges that are present in the compiler only solution. 1 We use the term "MIMD machine" to mean any architecture that guarantees loose fairness in thread scheduling so that threads not waiting on a programmer synchronization condition make forward progress.

Figures (17)
Fig. 1: SIMT-Induced Deadlock threads within the control flow paths) the execution of d same warp to diverge (i.e., follow different . However, they achieve this by serializing ifferent control-flow paths while restoring SIMD utilization by forcing divergent threads to reconverge as soon as possible (typically at an immediate postdominator point) [2], [5], [8 . This in turn creates implicit scheduling constraints for divergent threads within a warp. Therefore, when GPU kernel programmer intend code is written in such a way that the s divergent threads to communicate, these scheduling constraints can lead to surprising (from a program- mer perspective) d a multi-threaded p a MIMD architect eadlock and/or livelock conditions. Thus, rogram that is guaranteed to terminate on ure may not terminate on machines with current SIMT implementations (oy. hmed ElTantawy and Tor M. Aamod University of British Columbia {ahmede,aamodt} @ece.ubc.ca
Fig. 1: SIMT-Induced Deadlock threads within the control flow paths) the execution of d same warp to diverge (i.e., follow different . However, they achieve this by serializing ifferent control-flow paths while restoring SIMD utilization by forcing divergent threads to reconverge as soon as possible (typically at an immediate postdominator point) [2], [5], [8 . This in turn creates implicit scheduling constraints for divergent threads within a warp. Therefore, when GPU kernel programmer intend code is written in such a way that the s divergent threads to communicate, these scheduling constraints can lead to surprising (from a program- mer perspective) d a multi-threaded p a MIMD architect eadlock and/or livelock conditions. Thus, rogram that is guaranteed to terminate on ure may not terminate on machines with current SIMT implementations (oy. hmed ElTantawy and Tor M. Aamod University of British Columbia {ahmede,aamodt} @ece.ubc.ca
Fig. 3: Modified SIMT compliant Spin Lock
Fig. 3: Modified SIMT compliant Spin Lock
Algorithm 1 SIMT-Induced Deadlock Detection slice of the loop exit condition. If the loop exit conditions do not depend on a shared memory read operation that occurs inside the loop body then the loop cannot have a SIMT- induced deadlock. If a loop exit condition does depend on a shared memory read instruction Ip, we add Ig in the set of shared reads Shrdgeags on lines 4-7. A potential SIMT- induced deadlock exists if any of these shared memory reads can be redefined by divergent threads. The next steps of the algorithm detect these shared memory redefinitions.
Algorithm 1 SIMT-Induced Deadlock Detection slice of the loop exit condition. If the loop exit conditions do not depend on a shared memory read operation that occurs inside the loop body then the loop cannot have a SIMT- induced deadlock. If a loop exit condition does depend on a shared memory read instruction Ip, we add Ig in the set of shared reads Shrdgeags on lines 4-7. A potential SIMT- induced deadlock exists if any of these shared memory reads can be redefined by divergent threads. The next steps of the algorithm detect these shared memory redefinitions.
Algorithm 2 Safe Reconvergence Points loop exit is control dependent on the atomicCAS instruction, there are no shared memory write instructions that are parallel to, or reachable from, the loop exit. Therefore, no SIMT deadlock is detected.
Algorithm 2 Safe Reconvergence Points loop exit is control dependent on the atomicCAS instruction, there are no shared memory write instructions that are parallel to, or reachable from, the loop exit. Therefore, no SIMT deadlock is detected.
Fig. 4: SIMT-induced deadlock scenarios occurs if these indefinitely blocked paths must execute to enable the exit conditions of the looping threads. To avoid this, our compiler based SIMT deadlock elimination algorithm (ex- plained in more details in Section IV-A) replaces the backward edge of a loop identified by Algorithm | with two edges: a forward edge towards the loop’s SafePDom, and a backward edge from SafePDom to the loop header. This modification combined with the forced reconvergence constraint, guarantees that threads iterating in the loop wait at the SafePDom for threads executing other paths postdominated by SafePDom before attempting another iteration. Accordingly, SafePDom should postdominate the original loop exits, the redefining writes, and all control flow paths that could lead to redefining writes that are either reachable from the loop (lines 4-9 in Algorithm 2) or parallel to it (ines /0-/4 in Algorithm 2).
Fig. 4: SIMT-induced deadlock scenarios occurs if these indefinitely blocked paths must execute to enable the exit conditions of the looping threads. To avoid this, our compiler based SIMT deadlock elimination algorithm (ex- plained in more details in Section IV-A) replaces the backward edge of a loop identified by Algorithm | with two edges: a forward edge towards the loop’s SafePDom, and a backward edge from SafePDom to the loop header. This modification combined with the forced reconvergence constraint, guarantees that threads iterating in the loop wait at the SafePDom for threads executing other paths postdominated by SafePDom before attempting another iteration. Accordingly, SafePDom should postdominate the original loop exits, the redefining writes, and all control flow paths that could lead to redefining writes that are either reachable from the loop (lines 4-9 in Algorithm 2) or parallel to it (ines /0-/4 in Algorithm 2).
Algorithm 3 SIMT-Induced Deadlock Elimination it postdominates all reachable paths to the redefining writes (i.e., leading threads may only wait for lagging ones after they finish all iterations of the outer loop).
Algorithm 3 SIMT-Induced Deadlock Elimination it postdominates all reachable paths to the redefining writes (i.e., leading threads may only wait for lagging ones after they finish all iterations of the outer loop).
Fig. 5: SIMT-Induced Deadlock Elimination Steps
Fig. 5: SIMT-Induced Deadlock Elimination Steps
Fig. 6: MIMD-Compatible Reconvergence Mechanism Operation
Fig. 6: MIMD-Compatible Reconvergence Mechanism Operation
TABLE II: Code Configuration Encoding our generated CFG. This could be avoided if the elimination algorithm is applied at the SASS code generation stage. We also implemented AWARE in GPGPU-Sim 3.2.2 [53], [54]. We use the Tes Sim. However, scheduler with scheduler that we observed th aC2050 configuration released with GPGPU- we replaced the Greedy Then Oldest (GTO) a Greedy then Loose Round Robin (GLRR) forces loose fairness in warp scheduling as at unfairness in GTO leads to livelocks due to inter-warp de pendencies on locks 8. Modified GPGPU-Sim and LLVM codes can be found online [19].
TABLE II: Code Configuration Encoding our generated CFG. This could be avoided if the elimination algorithm is applied at the SASS code generation stage. We also implemented AWARE in GPGPU-Sim 3.2.2 [53], [54]. We use the Tes Sim. However, scheduler with scheduler that we observed th aC2050 configuration released with GPGPU- we replaced the Greedy Then Oldest (GTO) a Greedy then Loose Round Robin (GLRR) forces loose fairness in warp scheduling as at unfairness in GTO leads to livelocks due to inter-warp de pendencies on locks 8. Modified GPGPU-Sim and LLVM codes can be found online [19].
‘ig. 7: AWARE Virtualized Implementation TABLE I: Evaluated Kernels
‘ig. 7: AWARE Virtualized Implementation TABLE I: Evaluated Kernels
Fig. 8: Normalized Accumulative GPU Execution Time
Fig. 8: Normalized Accumulative GPU Execution Time
TABLE V: SSDE Evaluation on OpenMP Kernels
TABLE V: SSDE Evaluation on OpenMP Kernels
Fig. 9: Evaluation of the Static SIMT-Induced Deadlock Elimination on Tesla K20C GPU
Fig. 9: Evaluation of the Static SIMT-Induced Deadlock Elimination on Tesla K20C GPU
Fig. 11: Sensitivity to the TimeOut value (in cycles)
Fig. 11: Sensitivity to the TimeOut value (in cycles)
Fig. 10: Evaluation of the Adaptive Warp Reconvergence Mechanism using GPGPU-Sim
Fig. 10: Evaluation of the Adaptive Warp Reconvergence Mechanism using GPGPU-Sim
Fig. 12: Effect of AWARE Virtualization on Performance
Fig. 12: Effect of AWARE Virtualization on Performance

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