Wafer Level Integration of 3-D Heat Sinks in Power ICs
2017, IEEE Transactions on Electron Devices
https://doi.org/10.1109/TED.2017.2732733Abstract
In this paper, an innovative process flow developed to improve the thermal resistance of power ICs was presented. In this field, one of the major device failure mechanisms is related to the high temperatures reached during the working cycles due to the extremely critical electrical current densities. Therefore, heat transfer and dissipation are crucial aspects that need continuous improvements. Usual approaches to face this issue deal with package heat sinks design, solder selection, and wafer thinning. In this paper, a novel technological approach was settled, in which heat sinks microstructures were successfully integrated at wafer level stage on standard p-in diodes. To this aim, the bulk Si on the backside was partially replaced with Cu, a material characterized by a higher thermal conductivity material. Moreover, the well microstructures filled by Cu provide the advantage of wafer self-support, without requiring dedicated and more expensive thinning and handling technologies. An extensive characterization of the final devices was also carried out to evaluate the process and the thermal and electrical improvements. Finally, a failure analysis on selected devices was performed to identify any critical issue with the standard packaging process.
References (22)
- M. B. Karoui et al., "Effect of defects on electrical properties of 4H-SiC Schottky diodes," Mater. Sci. Eng., C, vol. 28, nos. 5-6, pp. 799-804, Jul. 2008.
- M. B. Karoui et al., "Influence of inhomogeneous contact in electrical properties of 4H-SiC based Schottky diode," Solid-State Electron., vol. 52, no. 8, pp. 1232-1236, Aug. 2008.
- L. Scaltrito et al., "Surface analysis and defect characterization of 4H-SiC wafers for power electronic device applications," Diamond Relat. Mater., vol. 12, nos. 3-7, pp. 1224-1226, Mar./Jul. 2003.
- L. Scaltrito et al., "Structural and electrical characterization of epitaxial 4H-SiC layers for power electronic device applications," Mater. Sci. Eng., B, vol. 102, nos. 1-3, pp. 298-303, Sep. 2003.
- D. Perrone, M. Naretto, S. Ferrero, L. Scaltrito, and C. F. Pirri, "4H-SiC Schottky barrier diodes using Mo-, Ti-and Ni-based contacts," Mater. Sci. Forum, vols. 615-617, pp. 647-650, Mar. 2009.
- K. Shili, M. B. Karoui, R. Gharbi, M. Abdelkrim, M. Fathallah, and S. Ferrero, "Series resistance study of Schottky diodes developed on 4H-SiC wafers using a contact of titanium or molybdenum," Micro- electron. Eng., vol. 106, pp. 43-47, Jun. 2013.
- D. B. Tuckerman and R. F. W. Pease, "High-performance heat sinking for VLSI," IEEE Electron Device Lett., vol. EDL-2, no. 5, pp. 126-129, May 1981.
- L. Ventola, L. Scaltrito, S. Ferrero, G. Maccioni, E. Chiavazzo, and P. Asinari, "Micro-structured rough surfaces by laser etching for heat transfer enhancement on flush mounted heat sinks," J. Phys., Conf. Ser., vol. 525, no. 1, p. 012017, 2014.
- Y. Yamada et al., "Pb-free high temperature solders for power device packaging," Microelectron. Rel., vol. 46, nos. 9-11, pp. 1932-1937, Sep./Nov. 2006.
- F. P. McCluskey, M. Dash, Z. Wang, and D. Huff, "Reliability of high temperature solder alternatives," Microelectron. Rel., vol. 46, nos. 9-11, pp. 1910-1914, Sep./Nov. 2006.
- Y. Yamada et al., "Reliability of wire-bonding and solder joint for high temperature operation of power semiconductor device," Microelectron. Rel., vol. 47, no. 12, pp. 2147-2151, Dec. 2007.
- S. Im and K. Banerjee, "Full chip thermal analysis of planar (2-D) and vertically integrated (3-D) high performance ICs," in IEDM Tech. Dig., Dec. 2000, pp. 727-730.
- M.-H. Liao, C.-P. Hsieh, and C.-C. Lee, "Systematic investigation of self-heating effect on CMOS logic transistors from 20 to 5 nm technology nodes by experimental thermoelectric measurements and finite element modeling," IEEE Trans. Electron Devices, vol. 64, no. 2, pp. 646-648, Feb. 2017.
- B. Dang, M. S. Bakir, and J. D. Meindl, "Integrated thermal-fluidic I/O interconnects for an on-chip microchannel heat sink," IEEE Electron Device Lett., vol. 27, no. 2, pp. 117-119, Feb. 2006.
- Z. Xu and J.-Q. Lu, "Through-silicon-via fabrication technologies, pas- sives extraction, and electrical modeling for 3-D integration/packaging," IEEE Trans. Semicond. Manuf., vol. 26, no. 1, pp. 23-34, Feb. 2013.
- C. Ricciardi et al., "Online portable microcantilever biosensors for salmonella enterica serotype enteritidis detection," Food Bioprocess Technol., vol. 3, no. 6, pp. 956-960, Dec. 2010.
- M. Cocuzza et al., "Silicon laterally resonant microcantilevers for absolute pressure measurement with integrated actuation and readout," J. Vac. Sci. Technol. B, Microelectron. Process. Phenom., vol. 26, no. 2, pp. 541-550, Mar. 2008.
- S. L. Marasso et al., "APEX protocol implementation on a lab-on- a-chip for SNPs detection," Microelectron. Eng., vol. 85, nos. 5-6, pp. 1326-1329, May/Jun. 2008.
- D. Balma et al., "Piezoelectrically actuated MEMS microswitches for high current applications," Microelectron. Eng., vol. 88, no. 8, pp. 2208-2210, Aug. 2011.
- S. M. Sze and M. -K. Lee, Semiconductor Devices: Physics and Technology. New York, NY, USA: Wiley, 2006.
- M. Motoyoshi and M. Koyanagi, "3D-LSI technology for image sensor," J. Instrum., vol. 4, no. 3, p. P03009, Mar. 2009.
- S. L. Marasso et al., "Back plate electroplating for high aspect ratio processes," Microelectron. Int., vol. 34, no. 2, pp. 69-74, 2017.