A Low-Complexity Edward-Curve Point Multiplication Architecture

Applied Sciences, 2023

This article presents an area-aware unified hardware accelerator of Weierstrass, Edward, and Huff curves over � � ( 2 233 ) for the point multiplication step in elliptic curve cryptography (ECC). The target implementation platform is a field-programmable gate array (FPGA). In order to explore the design space between processing time and various protection levels, this work employs two different point multiplication algorithms. The first is the Montgomery point multiplication algorithm for the Weierstrass and Edward curves. The second is the Double and Add algorithm for the Binary Huff curve. The area complexity is reduced by efficiently replacing storage elements that result in a 1.93 times decrease in the size of the memory needed. An efficient Karatsuba modular multiplier hardware accelerator is implemented to compute polynomial multiplications. We utilized the square arithmetic unit after the Karatsuba multiplier to execute the quad-block variant of a modular inversion, which preserves lower hardware resources and also reduces clock cycles. Finally, to support three different curves, an efficient controller is implemented. Our unified architecture can operate at a maximum of 294 MHz and utilizes 7423 slices on Virtex-7 FPGA. It takes less computation time than most recent state-of-the-art implementations. Thus, combining different security curves (Weierstrass, Edward, and Huff) in a single design is practical for applications that demand different reliability/security levels.

International Journal for Information Security Research

Elliptic Curve Cryptography (ECC), provides all public key cryptographic primitives like digital signatures and key agreement algorithms/protocols in a constrained applications such as wireless sensor networks and radio frequency identification networks (RFIDs). In order to achieve digital signatures and key agreements, point/scalar multiplication is necessary to perform. However, we demonstrate the hardware architecture of elliptic curve point multiplication for low area constrained applications over binary (2) field with = 233 bit field size. The lower area is achieved, by using single hybrid karatsuba multiplier for both squarer and multiplication computations. The novel architecture is modeled in Verilog (HDL) using Xilinx (ISE) design tool and synthesized for Virtex 7 fieldprogrammable-gate-array (FPGA). Moreover, it achieves a maximum operational frequency of 157MHz and utilizes only 11849 FPGA slices.

Embedded systems find applications in fields such as defense, communications, industrial automation and many more. For majority of these applications, security is a vital issue. Cryptography plays an important role in providing data security. Until recently, symmetric key encryption schemes were used for a majority of these applications. Now however, asymmetric key encryption schemes such as Elliptic curve cryptography are gaining popularity as they require less computational power and memory and are still capable of providing equivalent security when compared to their counterparts. The authors of this paper have implemented scalar multiplication, the most time consuming operation in elliptic curve cryptography using binary non-adjacent form algorithm. The results of the software implementation have been presented in section-4. Methodology to improve the performance of the scalar multiplication by use of hardware accelerators has also been presented in this paper.

2008 International Conference on Field-Programmable Technology, 2008

In this paper a processor that supports elliptic curve cryptographic applications over GF (2 m ) is proposed. The proposed structure is capable of calculating point multiplication and addition using a single coordinate to contain the point information. This compression allows for a better usage of the bandwidth resources. For the point multiplication procedure, all coordinate pre-calculations are completely avoided. This design was successful prototyped on a reconfigurable device for the field GF (2 163 ). Experimental results suggest that point multiplication can be performed in 144μs and point affine addition in 1.02μs. Comparing with the related work, a 5 times speedup is obtained for point addition and multiplication. The presented design offers a well balanced area-time performance when compared with existent elliptic curve point multiplication specific processors.

2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2020

This work presents a hardware accelerator, for the optimization of latency and area at the same time, to improve the performance of point multiplication process in Elliptic Curve Cryptography. In order to reduce the overall computation time in the proposed 2-stage pipelined architecture, a rescheduling of point addition and point doubling instructions is performed along with an efficient use of required memory locations. Furthermore, a 41-bit multiplier is also proposed. Consequently, the FPGA and ASIC implementation results have been provided. The performance comparison with state-of-the-art implementations, in terms of latency and area, proves the significance of the proposed accelerator.

Microprocessors and Microsystems, 2004

A fast parallel architecture for the implementation of elliptic curve scalar multiplication over binary fields is presented. The proposed architecture is implemented on a single-chip FPGA device using parallel strategies that trades area requirements for timing performance. The results achieved show that our proposed design is able to compute GF(2191) elliptic curve scalar multiplication operations in 63 ms. q .mx (N.A. Saqib); adiaz@ cs.cinvestav.mx (A. Díaz-Péerez).

Lecture Notes in Computer Science, 2009

Abstract. Hardware acceleration of cryptographic algorithms is beneficial be-cause considerable performance improvements can be attained compared to software implementations. Thus, hardware implementations can be used in crit-ical applications requiring high encryption or ...

PloS one, 2017

In this paper, we propose a novel parallel architecture for fast hardware implementation of elliptic curve point multiplication (ECPM), which is the key operation of an elliptic curve cryptography processor. The point multiplication over binary fields is synthesized on both FPGA and ASIC technology by designing fast elliptic curve group operations in Jacobian projective coordinates. A novel combined point doubling and point addition (PDPA) architecture is proposed for group operations to achieve high speed and low hardware requirements for ECPM. It has been implemented over the binary field which is recommended by the National Institute of Standards and Technology (NIST). The proposed ECPM supports two Koblitz and random curves for the key sizes 233 and 163 bits. For group operations, a finite-field arithmetic operation, e.g. multiplication, is designed on a polynomial basis. The delay of a 233-bit point multiplication is only 3.05 and 3.56 μs, in a Xilinx Virtex-7 FPGA, for Koblitz...

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Proceedings of the 2nd International Conference on Information Systems Security and Privacy, 2016

Elliptic curve cryptography (ECC) plays a vital role in passing secure information among different wireless devices. This paper presents a fast, high-performance hardware implementation of an ECC processor over binary field GF(2 m) using a polynomial basis. A high-performance elliptic curve point multiplier (ECPM) is designed using an efficient finite-field arithmetic unit in affine coordinates, where ECPM is the key operation of an ECC processor. It has been implemented using the National Institute of Standards and Technology (NIST) recommended curves over the field GF(2 163). The proposed design is synthesized in field-programmable gate array (FPGA) technology with the VHDL. The delay of ECPM in a modern Xilinx Kintex-7 (28-nm) technology is 1.06 ms at 306.48 MHz. The proposed ECC processor takes a small amount of resources on the FPGA and needs only 2253 slices without using any DSP slices. The proposed design provides nearly 50% better delay performance than recent implementations.