When are multiple gate errors significant in logic circuits?

Circuits, Systems, and Signal Processing, 2020

The reliability evaluation of logic circuits is an essential step in the computer-aided design flow of emerging integrated circuits (IC). Due to the increased process variation effects in submicron IC technologies, reliability evaluation should include the transistor-level faults' modeling and analysis. In this paper, a two-step reliability evaluation method was developed. In the first step, the gate error probability (in a matrix form) was computed based on transistor fault modeling. In the second step, the circuit's graph was traversed in topological order. Meanwhile, for each gate, the probability of the gate's output to be in 16 possible states was computed using the gate error probability matrix (calculated in the first step) and the corresponding gate inputs' probability matrices. The reliability of the circuit's outputs was extracted from the related 16-state probability matrix. Furthermore, the reconvergent fan-out problem was handled using the concept of correlation coefficients. Various simulations were performed on ISCAS 89 and LGSynth91 benchmark circuits. Compared with Monte-Carlo as a reference method, the results indicated a < 3% average error on reliability estimation. Furthermore, the estimation error and algorithm runtime of the proposed method significantly decreased in comparison with some state-of-the-art methods.

Microelectronics Journal, 2010

Soft errors due to cosmic radiations are the main reliability threat during lifetime operation of digital systems. Fast and accurate estimation of soft error rate (SER) is essential in obtaining the reliability parameters of a digital system in order to balance reliability, performance, and cost of the system. Previous techniques for SER estimation are mainly based on fault injection and random simulations. In this paper, we present an analytical SER modeling technique for ASIC designs that can significantly reduce SER estimation time while achieving very high accuracy. This technique can be used for both combinational and sequential circuits. We also present an approach to obtain uncertainty bounds on estimated error propagation probability (EPP) values used in our SER modeling framework. Comparison of this method with the Monte-Carlo fault injection and simulation approach confirms the accuracy and speed-up of the presented technique for both the computed EPP values and uncertainty bounds.

Proceedings International Conference on Dependable Systems and Networks

This paper examines the effect of technology scaling and microarchitectural trends on the rate of soft errors in CMOS memory and logic circuits. We describe and validate an end-to-end model that enables us to compute the soft error rates (SER) for existing and future microprocessor-style designs. The model captures the effects of two important masking phenomena, electrical masking and latchingwindow masking, which inhibit soft errors in combinational logic. We quantify the SER in combinational logic and latches for feature sizes from 600nm to 50nm and clock rates from 16 to 6 fan-out-of-4 delays. Our model predicts that the SER per chip of logic circuits will increase eight orders of magnitude by the year 2011 and at that point will be comparable to the SER per chip of unprotected memory elements. Our result emphasizes the need for computer system designers to address the risks of SER in logic circuits in future designs.

IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings.

Soft errors are functional failures resulting from the latching of single-event transients (transient voltage fluctuations at a logic node or SETs) caused by high-energy particle strikes or electrical noise. Traditionally, they have been deemed to be a problem in memory structures, for which effective techniques (such as error correcting codes) are well known. However, due to technology scaling and reduced supply voltages, they are expected to increase by several orders of magnitude in logic circuits. Existing circuit and architectural approaches to addressing soft errors in logic circuits have appreciable area/cost, performance, and/or energy overheads or are limited to particular types of circuits (combinational or sequential). We present a very efficient and systematic error masking technique that uses the same circuitry to cope with soft errors in combinational and sequential circuits. It prevents an SET pulse of width less than approximately half of the slack available in the propagation path from latching and turning into a soft error. The SET is masked without additional delay and within the clock cycle time in an area-and energy-efficient manner, which makes this technique attractive for commodity as well as reliabilitycritical applications. Our technique also tolerates soft errors in the overhead circuitry, which we minimize through clustering. Application of our technique to ISCAS85 benchmark circuits yields an average SER reduction of 70.93% with an average area overhead of only 11.98%.

2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems, 2008

Soft errors due to radiation are expected to increase in nanoelectronic circuits. Methods to reduce system failures due to soft errors include use of redundancy and making circuit elements robust such that soft errors do not upset signal values. Recent works have noted that electronic circuits have partial intrinsic immunity to soft errors since single event upsets on a large percentage of signal lines do not cause errors on circuit outputs. Using ISCAS-89 benchmark circuits we present experimental evidence that the partial immunity to single event upsets is in most cases due to redundancy in the circuits and thus immunity to soft errors may not be available in irredundant circuits. Thus goals on immunity to soft errors may not be achievable in highly optimized circuits without adding circuit redundancy and/or relaxing the requirements on system failures due to soft errors.

Design, Automation, and Test in Europe, 2009

Soft errors in combinational and sequential elements of digital circuits are an increasing concern as a result of technology scaling. Several techniques for gate and latch hardening have been proposed to synthesize circuits that are tolerant to soft errors. However, each such technique has associated overheads of power, area, and performance. In this paper, we present a new methodology to compute the failures in time (FIT) rate of a sequential circuit where the failures are at the system-level. System-level failures are detected by monitors derived from functional specifications. Our approach includes efficient methods to compute the FIT rate of combinational circuits (CFIT), incorporating effects of logical, timing, and electrical masking. The contribution of circuit components to the FIT rate of the overall circuit can be computed from the CFIT and probabilities of system-level failure due to soft errors in those elements. Designers can use this information to perform Pareto-optimal hardening of selected sequential and combinational components against soft errors. We present experimental results demonstrating that our analysis is efficient, accurate, and provides data that can be used to synthesize a low-overhead, low-FIT sequential circuit.

Soft errors, due to cosmic radiations, are one of the major challenges for reliable VLSI designs. In this paper, we present a symbolic framework to model soft errors in both synchronous and asynchronous designs. The proposed methodology utilizes Multiway Decision Graphs (MDGs) and glitch-propagation sets (GP sets) to obtain soft error rate (SER) estimation at gate level. This work helps mitigate design for testability (DFT) issues in relation to identifying the controllable and the observable circuit nodes, when the circuit is subject to soft errors. Also, this methodology allows designers to apply radiation tolerance techniques on reduced sets of internal nodes. To demonstrate the effectiveness of our technique, several ISCAS89 sequential and combinational benchmark circuits, and multiple asynchronous handshake circuits have been analyzed. Results indicate that the proposed technique is on average 4.29 times faster than the best contemporary state-of-the-art techniques. The proposed technique is capable to exhaustively identify soft error glitch propagation paths, which are then used to estimate the SER. To the best of our knowledge, this is the first time that a decision diagram based soft error identification approach is proposed for asynchronous circuits.

International Journal of VLSI Design & Communication Systems, 2015

Through technology development, VLSI fabrication is becoming smaller in size which causes much sensitivity of VLSI circuit to noise effects especially soft error. In this paper, we present a method to mitigate soft error in combinational logic gates based on 65 nm technology that is able to reduce the possibility of noise propagation in combinational logic gate. We evaluate our result based on ISCAS 85 benchmark circuit. Through DFS algorithm and using analytical model derived by stimulation of each combinational logic gate in transistor layer, soft error is processed in paths of ISCAS 85 circuit benchmark and a single buffer logic gate is added to the end of the paths that have more potential to be affected by soft error. Therefore, possibility of soft error distribution through circuit benchmark is measured. The buffer gates that mitigate soft errors on the benchmark paths are kept and others are eliminated. After processing, new circuit benchmark is available that includes added buffer logic gate to only critical paths. This is more reliable than initial ISCAS85 circuit benchmark in terms of illuminating soft error. The results show that possibility of soft error distribution is reduced intelligently and due to adding buffer gate to just suspicious paths of benchmark, power and delay are optimum.

2017

A new method of evaluating the reliability of combinational circuits is proposed, this method uses two levels of characterisation: a Stochastic Fault Model (SFM) of the component library and a design-specific Critical Vector Model (CVM). The idea is to move the high-complexity problem of stochastic characterisation of parameters into the generic part of the design process, and do it just once for a great number of the specific designs. The SFM captures variations of the vector of parameters of a library component fault model, those causing a transient fault at the component output; it is meant to be supplied by the foundry, similar to timing library files. The CVM is derived by a limited number of simulation runs on the specific design, and represents the boundary between the erroneous and error-free operation, w.r.t. the vector of parameters of each component. The probability of error-free operation is subsequently calculated by jointly using SFM and CVM. The method is demonstrated...