Ramen Dutta

University of Twente, Faculty EEMCS, Adjunct

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Analog and RF circuit design with experience of various wireless communication applications.

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Ultra low power and interference robust transceiver techniques for wireless sensor networks

Wireless sensor networks (WSNs) have the potential to build breakthrough technologies for a varie... more Wireless sensor networks (WSNs) have the potential to build breakthrough technologies for a variety of applications to improve human life. Some of the important applications are prevention, prediction and rescue of disasters, medical study and cure, improve the energy efficiency of homes and industries and study environments in remote places. These applications desire an ultra low power sensor node to extend the battery life, so that minimum or zero maintenance is required after initial installation. With the advancement of CMOS technology, power consumption of processors and semiconductor memories has reduced drastically. However, the radio transceiver power consumption has not experienced much power reduction because of its RF analog circuits. This makes the transceiver the bottleneck with respect to lifetime in existing sensor nodes. Another growing challenge for the sensor node transceiver is its interference robustness. Therefore there is a need of ultra low energy and interference robust wireless transceivers to enable WSNs to thrive in several applications which are not yet successful. This thesis targets an energy optimized and interference-robust radio communication system for WSNs. Special focus is given to the receiver, as the receiver is either always ON or ON for more time than the transmitter for duty-cycled radio and hence it is the critical part of the transceiver performance both in terms of power reduction and interference mitigation. A system level optimization of the transceivers is carried out, and circuit techniques are proposed to reduce the receiver power consumption. sensornetwerken gebaseerd op andere communicatiestandaarden te verbeteren. v Contents Contents vii List of Figures xi Nomenclature xiv acknowledgement xiv B.1 Chirp synchronization circuit block diagram for the chirped-LO

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Low power radio communication platform for wireless sensor network

Wireless sensor networks are predicted to be the most versatile, popular and useful technology in... more Wireless sensor networks are predicted to be the most versatile, popular and useful technology in the near future. A large number of applications are targeted which will hugely benefit from a network of tiny computers with few sensors, radio communication platform, intelligent networking and controller programs. Few of these applications which look very attractive at this point of time are medical (such as patient monitoring), structure monitoring (such as bridges, coal mine), logistics and transport, control and rescue operation in natural hazards (like firefighters), building management (security, temperature control), wild life/ ocean life monitoring, traffic control, area monitoring, intruder tracking etc.

An Ultra Low Energy FSK Receiver With In-Band Interference Robustness Exploiting a Three-Phase Chirped LO

IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2014

ABSTRACT An ultra-low-energy Binary Frequency Shift Keying (BFSK) receiver is proposed. It featur... more ABSTRACT An ultra-low-energy Binary Frequency Shift Keying (BFSK) receiver is proposed. It features improved in-band interference tolerance by chirping the transmission frequency. To reduce the receiver power consumption, a novel three-phase passive mixer along with a three stage digitally controlled ring oscillator is proposed, while still allowing quadrature detection. A mixer-first direct conversion receiver architecture moves the required gain to lowest frequency and lowest bandwidth to reduce power consumption. A low power flip-flop based BFSK demodulator is proposed that reduces the baseband power further. The receiver is designed and fabricated in a 65 nm complementary metal–oxide–semiconductor process. It consumes 219 $mu {rm W}$ from 1.2 V power supply, while having a sensitivity of $-70~{rm dBm}$ for a bit error rate of 0.1% at 2.4 GHz. Except the off-chip 64 MHz clock generation, the total receiver requires 27 pJ/bit. Using a chirped clock spreading of 360 MHz and chirp repetition rate of 1 MHz, it can tolerate up to $-8~{rm dB}$ signal to interference ratio for all interferer frequencies. This is 13.5 dB better than previously reported in literature and 12 dB better than ideal noncoherent BFSK receiver interference robustness.

Choosing optimum noise figure and data rate in wireless sensor network radio transceivers

To reduce the energy consumption in wireless sensor network transceivers, we propose an approach ... more To reduce the energy consumption in wireless sensor network transceivers, we propose an approach which combines two tradeoffs. The first tradeoff is between the receiver sensitivity and transmitter output power. The second one is the duty cycle and data rate of the transceiver. The combined approach gives us the optimum choice of noise figure and data rate for a given application and transceiver architecture. Considering a typical transceiver architecture and perfectly synchronized system, we show that the energy consumption can indeed be reduced with this approach compared to choosing either data rate or noise figure arbitrarily. Moreover, in case of a wakeup receiver architecture and slot based MAC protocol, applying this method, we show that there is a different combination of optimum data rate and noise figure value for the wakeup receivers to minimize the wakeup energy.

Flip-Flops for Accurate Multiphase Clocking: Transmission Gate Versus Current Mode Logic

Dynamic transmission gate (DTG) flip-flops (FFs) (DTG-FFs) and current mode logic (CML) FFs (CML... more Dynamic transmission gate (DTG) flip-flops (FFs)
(DTG-FFs) and current mode logic (CML) FFs (CML-FFs) are
compared targeting power efficient multiphase clock generation
with low phase error. The effect of component mismatches on
multiphase clock timing inaccuracies is modeled and compared,
using the product of mismatch-induced jitter variance and power
consumption as a figure-of-merit (FOM). Analytical equations are
derived to estimate the jitter–power FOM for DTG-FF- and CMLFF-
based dividers. Simulations confirm the trends predicted by
the equations and show that DTG-FFs achieve a better FOM than
CML-FFs. The advantage increases for CMOS processes with
smaller feature size and for a lower input frequency compared
to f_T .

Optimized Stage Ratio of Tapered CMOS Inverters for Minimum Power and Mismatch Jitter Product

In this paper, an optimum stage ratio (tapering factor) for a tapered CMOS inverter chain is deri... more In this paper, an optimum stage ratio (tapering factor) for a tapered CMOS inverter chain is derived to minimize the product of power dissipation and jitter variance due to device mismatch. Analysis shows that this optimum stage ratio (2.4) is lower than that of minimum delay (3.6) and minimum power-delay (6.35) product. This analysis is verified by simulation results using standard 180nm as well as 90nm CMOS technology. Knowledge of the optimum stage ratio helps to design low power low mismatch jitter buffers for multi phase clock generation circuits that can drive large load capacitances. Index Terms-tapering factor, stage ratio, CMOS inverter, mismatch jitter, multiphase clock, low power, figure of merit.

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Performance of chirped-FSK and chirped-PSK in the presence of partial-band interference

Journal of Physics: Conference Series, 2011

To improve interference robustness of wireless communication, spread spectrum techniques are ofte... more To improve interference robustness of wireless communication, spread spectrum techniques are often used. We use the chirp spreading technique along with FSK and PSK binary modulation schemes to obtain interference robust radio communication. The performance of chirped-FSK and chirped-PSK modulation through a white gaussian noise channel is simulated assuming a synchronized clock between transmitter and the receiver. We analyzed and simulated the error probability (BER) of the overall system in the presence of partial band of interference in the channel. The simulated BER is close to the estimated BER and they prove the superior performance of chirp-based modulation in the presence of interference.

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A Low Power Architecture to Extend the Tuning Range of a Quadrature Clock

A low power architecture to extend the frequency range of quadrature clock is proposed. This arch... more A low power architecture to extend the frequency range of quadrature clock is proposed. This architecture is based on a series of dividers. It can enhance the lower frequency limit of a Quadrature Voltage Controlled Oscillator (QVCO) clock to any arbitrarily small frequency. Based on the architecture a design is shown which enhances the low frequency range up to -90% of the center frequency, assuming the QVCO tuning range is +20%. The dividers are made of Dynamic Transmission Gate Logic (DTGL) to reduce power consumption. Simulation result shows that the power consumption of the extender circuit, excluding the QVCO, is 2.1 mW from 1.2 V supply voltage at 3 GHz input frequency in 90 nm CMOS technology. The output jitter contribution by this circuit is 2 ps and 0.15 ps for mismatch and thermal noise respectively. Maximum output frequency achieved is 4.8 GHz for differential clock and 2.4 GHz for quadrature clock.

Jitter-Power minimization of digital frequency synthesis architectures

Cognition, Technology & Work, 2011

Digital intensive architectures allow for flexibly programmable frequency synthesis. Timing jitte... more Digital intensive architectures allow for flexibly programmable frequency synthesis. Timing jitter and/or phase noise is an important quality criterion for synthesizers. This paper reviews fundamental limitations for jitter in digital frequency architectures, aiming at finding a basis to compare alternative architectures and optimize jitter performance. It motivates why the product of jitter variance and power consumption is a useful figure of merit (FoM) for optimization, based on fundamental physical limitations. Applying this FoM to multi-phase clock generation leads to the conclusion that circuits with low delay are preferred, favoring a shift register architecture ("ring counter") over a Delay Locked Loop. For a PLL a Jitter-Power FoM is also defined and we show that significant improvements have been made during recent years.

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