Gus Uht

University of Rhode Island, Electrical, Computer, and Biomedical Engineering, Faculty Member

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Ideograph/ideogram: framework/hardware for eager evaluation

International Symposium on Microarchitecture, Nov 30, 1990

Abstract Ideograph integrates data and control dependencies into a unified representation and is ... more

The integrated computer engineering design (ICED) curriculum

A new undergraduate computer engineering curriculum, ICED, is being introduced at the University ... more A new undergraduate computer engineering curriculum, ICED, is being introduced at the University of Rhode Island. The main feature of the curriculum is a design project spanning the last three years of the major. This gives continuity to a student's studies: they will always know why they are l e arning a particular topic, and how it ts into the big picture. It also introduces them to long-term projects, and the requisite good documentation and communication habits necessary for its completion. The project to be undertaken is the design, simulation and construction of a computer and its compiler, including the design of its instruction set. Further, the various students' computers will be networked together during the nal integration phase of the project. Thus, several aspects of computer architecture are treated in depth. Students will learn to make hardware/software design tradeo s, as well as get hands-on experience with hardware. A key element of the design experience is the use of modern CAD tools. The Mentor Graphics CAD tool suite will be used throughout the curriculum. By standardizing on one s e t o f t o ols, the time for the students to learn the tools is amortized over the entire curriculum. The curriculum has received funding from the National Science F oundation, and has been formally approved by the University. Students began the curriculum in Fall, 1997. This paper gives the rationale of ICED in depth, and describes the core courses, their activities and use of CAD tools, and how they interrelate to achieve the goals. The current status of ICED is also reviewed.

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Modelling The Effects Of Instruction Queue Loading On A Static Instruction Stream Micro-architecture

Increased processor performance requires the exploitation of the parallelism that exists within t... more Increased processor performance requires the exploitation of the parallelism that exists within the instruction stream and within the processor itself: A static instruction stream micro-architecture, CONDEL, extracts and uses the machine instruction level concurrency implicit in the instruction stream. A major source of intmprocessor parallelism is the overlap of instruction execution with instruction loading. The effect of several methods of

A theory of reduced and minimal procedural dependencies

IEEE Computer Society Press eBooks, Mar 1, 1995

ABSTRACT

Disjoint eager execution: an optimal form of speculative execution

International Symposium on Microarchitecture, Dec 1, 1995

Data path issues in a highly concurrent machine

ACM Sigmicro Newsletter, Dec 10, 1992

ABSTRACT

Hardware extraction of low-level concurrency from sequential instruction streams (parallelism, implementation, architecture, dependencies, semantics)

The thesis presents hardware solutions to low-level (semantic) concurrency extraction. In the fir... more The thesis presents hardware solutions to low-level (semantic) concurrency extraction. In the first solution the focus is on reducing control-flow inhibitors of concurrency in sequential instruction streams. A theory of reduced procedural dependencies is outlined, based on traditional code's branch domains (the code between a branch and its target), and a hardware execution algorithm is described. In the second solution, the focus is on the reduction of data-flow inhibitors of concurrency in sequential instruction streams. A set of semantic dependencies are demonstrated to be necessary and sufficient for sequential instruction streams. This minimal set, combined with restrictive array accesses, is used by the second solution. The reduced procedural dependency algorithm of the first solution is combined with a new reduced data dependency algorithm to yield a new (more costly) machine model executing standard sequential code in a data-flow-like manner. Also considered is a conceptually simple form of branch prediction used in conjunction with the second model. The two solutions are evaluated in terms of performance and hardware cost and delay. Different variations of data and procedural dependency models are simulated using a wide range of benchmarks as input. The performance results are presented and analyzed, showing both gains and areas for further improvement.

Understanding Eager Evaluation of Imperative Instruction Streams, Part 1

Teradactyl: an Easy-to-Use Supercomputer

Since Ada Lovelace, using supercomputers has been much harder than building them. Compilers can o... more Since Ada Lovelace, using supercomputers has been much harder than building them. Compilers can only occasionally automatically parallelize interesting programs. Researchers spend years developing efficient code. We propose to turn the supercomputing norm on its head: we won't use software to adapt to hardware idiosyncrasies, instead we'll make software easy with sophisticated hands-off supercomputers. We want to let scientists concentrate on science, instead of scheduling loop iterations on parallel hardware. In this paper we propose an alternative: using our Teradactyl supercomputer architecture, based on our successful Levo processor (see http://www.jilp.org , Volume 5, August). We describe and analyze Teradactyl within.

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Exploring Prefetching, Pre-Execution and Branch Outcome Streaming for In-Memory Database Lookups

IEEE Computer Architecture Letters, 2019

Lookup operations for in-memory databases are heavily memory-bound because they often rely on poi... more Lookup operations for in-memory databases are heavily memory-bound because they often rely on pointer-chasing linked data structure traversals. They are also branch heavy with branches that are hard-to-predict due to random key lookups. In this study, we show that although cache misses are the primary bottleneck for these applications, without a method for eliminating the branch mispredictions, only a small fraction of the performance benefit is achieved through prefetching. We propose the Node Tracker (NT), a novel programmable prefetcher/pre-execution unit that is highly effective in exploiting inter key-lookup parallelism to improve single-thread performance. We extend the NT with branch outcome streaming (BOS) to reduce branch mispredictions and show that NT with BOS can achieve an extra 3x speedup. Finally, we evaluated the NT as a pre-execution unit and show that we can further improve the performance in both singleand multi-threaded execution modes.

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Hardware Extraction of Low-Level Concurrency from Serial Instruction Streams

International Conference on Parallel Processing, 1986

It has been demonstrated that low-level concurrent machines may extract a significant amount of c... more It has been demonstrated that low-level concurrent machines may extract a significant amount of concurrency from code. This is particularly true when compiler-based parallelization enhancements are used in conjunction with the hardware. However, this has been demonstrated without tailoring a compiler specifically to the machine. Machine-specific and general optimizations applied to the code at compile time may have a large effect on the total system performance obtainable. In this paper, such transformations are developed or identified, described, and evaluated. Significant performance gains resulting from the transformations are demonstrated. This paper is partially based on work originally developed in [15]. Part of this work may appear in a journal article currently undergoing review [21].

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Cover feature - Going beyond worst-case specs with teatime

Ieee Computer Society, 2004

Exploitation of low-level concurrency : an implementation and architecture

Memory Error Correction without ECC

Interlaced Data/Regeneration for Memory Refresh

Hierarchical Computation Server: Goals, Architecture, and Issues

Dynamic Instruction Substitution: A Technique of Minimizing Data Dependencies for Memory References

Ideograph and Minimal Procedural Dependencies

Integrated Approach to Concurrent Code Execution with respect to Instruction Scheduling and Memory Reference Disambiguation

System for Extracting Low-Level Concurrency from Serial Instruction Streams

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