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Cristian Gingu

University Politehnica of Bucharest, Faculty of Electronics, Telecommunications and IT, Alumnus

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Papers by Cristian Gingu

Energy-Aware Memory Management for Embedded Multimedia Systems

Chapman & Hall/CRC Computer & Information Science Series, 2011

In real-time data-intensive multimedia processing applications, data transfer and storage signifi... more In real-time data-intensive multimedia processing applications, data transfer and storage significantly influence, if not dominate, all the major cost parameters of the design space-namely energy consumption, performance, and chip area. This paper presents an electronic design automation (EDA) methodology for the high-level design of hierarchical memory architectures in embedded data-intensive applications, mainly in the area of multidimensional signal processing. Different from the previous works, the problems of data assignment to the memory layers, of mapping the signals into the physical memories, and of banking the on-chip memory are addressed in a consistent way, based on the same formal model. This memory management framework employs techniques specific to the integral polyhedra based dependence analysis. The main design target is the reduction of the static and dynamic energy consumption in the hierarchical memory subsystem.

A Reconfigurable Neural Network ASIC for Detector Front-End Data Compression at the HL-LHC

IEEE Transactions on Nuclear Science, 2021

Despite advances in the programmable logic capabilities of modern trigger systems, a significant ... more Despite advances in the programmable logic capabilities of modern trigger systems, a significant bottleneck remains in the amount of data to be transported from the detector to off-detector logic where trigger decisions are made. We demonstrate that a neural network autoencoder model can be implemented in a radiation tolerant ASIC to perform lossy data compression alleviating the data transmission problem while preserving critical information of the detector energy profile. For our application, we consider the high-granularity calorimeter from the CMS experiment at the CERN Large Hadron Collider. The advantage of the machine learning approach is in the flexibility and configurability of the algorithm. By changing the neural network weights, a unique data compression algorithm can be deployed for each sensor in different detector regions, and changing detector or collider conditions. To meet area, performance, and power constraints, we perform a quantizationaware training to create an optimized neural network hardware implementation. The design is achieved through the use of high-level synthesis tools and the hls4ml framework, and was processed through synthesis and physical layout flows based on a LP CMOS 65 nm technology node. The flow anticipates 200 Mrad of ionizing radiation to select gates, and reports a total area of 3.6 mm 2 and consumes 95 mW of power. The simulated energy consumption per inference is 2.4 nJ. This is the first radiation tolerant on-detector ASIC implementation of a neural network that has been designed for particle physics applications.

Optimization of memory banking in embedded multidimensional signal processing applications

2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015

Hierarchical memory organizations are used in embedded systems to reduce energy consumption and i... more Hierarchical memory organizations are used in embedded systems to reduce energy consumption and improve performance by assigning the frequently-accessed data to the low levels of memory hierarchy. Within a given level of hierarchy, energy and access times can be further reduced by memory banking. This paper addresses the problem of banking optimization, presenting a dynamic programming approach that takes into account all three major design objectives - energy consumption, performance, and die area, letting the designers decide on their relative importance for a specific project. The time complexity is independent of the size of the storage access trace and of the memory size - a significant advantage in terms of computation speed when these two parameters are large.

The MINERνA data acquisition system and infrastructure

MINERνA (Main INjector ExpeRiment ν-A) is a new few-GeV neutrino cross section experiment that be... more MINERνA (Main INjector ExpeRiment ν-A) is a new few-GeV neutrino cross section experiment that began taking data in the FNAL NuMI (Fermi National Accelerator Laboratory Neutrinos at the Main Injector) beam-line in March of 2010. MINERνA employs a fine-grained scintillator detector capable of complete kinematic characterization of neutrino interactions. This paper describes the MINERνA data acquisition system (DAQ) including the read-out electronics, software, and computing architecture.

Leakage-aware scratch-pad memory banking for embedded multidimensional signal processing

2014 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 2014

Partitioning a memory into multiple banks that can be independently accessed is an approach mainl... more Partitioning a memory into multiple banks that can be independently accessed is an approach mainly used for the reduction of the dynamic energy consumption. When leakage energy comes into play as well, the idle memory banks must be put in a low-leakage 'dormant' state to save static energy when not accessed. The energy savings must be large enough to compensate the energy overhead spent by changing the bank status from active to dormant, then back to active again. This paper addresses the problem of energy-aware on-chip memory banking, taking into account-during the exploration of the search space-the idleness time intervals of the data mapped into the memory banks. As on-chip storage, we target scratch-pad memories (SPMs) since they are commonly used in embedded systems as an alternative to caches. The proposed approach proved to be computationally fast and very efficient when tested for several data-intensive applications, whose behavioral specifications contain multidimensional arrays as main data structures.

Energy-aware scratch-pad memory partitioning for embedded systems

Fifteenth International Symposium on Quality Electronic Design, 2014

ABSTRACT Hierarchical memory organizations are used in embedded systems to reduce energy consumpt... more ABSTRACT Hierarchical memory organizations are used in embedded systems to reduce energy consumption and improve performance by exploiting the non-uniformity of memory accesses and assigning the frequently-accessed data to the low levels of memory hierarchy. Moreover, within a given level, energy can be further reduced and performance further enhanced by memory partitioning - whose principle is to divide the address space in several smaller blocks and to map these blocks to physical memory banks. Scratch-pad memories (SPMs) offer a good compromise - as on-chip storage in embedded systems - when taking into account performance, energy consumption, and die area. This paper addresses the problem of optimizing the partitioning of SPMs. Different from previous techniques, the cost function takes into account all the three major design objectives - energy consumption, performance, and die area, letting the designers decide on their relative importance for a specific project. The proposed approach proved to be computationally fast and very efficient when tested for several data-intensive applications, whose behavioral specifications contain multidimensional arrays as main data structures.

Design space exploration for low-power memory systems in embedded signal processing applications

2013 IEEE 19th International Conference on Embedded and Real-Time Computing Systems and Applications, 2013

ABSTRACT This paper presents an energy-aware electronic design automation (EDA) methodology for t... more ABSTRACT This paper presents an energy-aware electronic design automation (EDA) methodology for the system-level exploration of hierarchical storage organizations, focusing mainly on data-intensive signal processing applications. Starting from the high-level behavioral specification of a given application, several memory management tasks are addressed in a common algebraic framework, using data-dependence analysis techniques similar to those used in modern compilers. Within this memory management software system, the designer can explore different algorithmic specifications functionally equivalent, by computing their minimum storage requirements. The system can perform an exploration based on energy consumption of signal assignments to the off- and on-chip memory layers, followed by a storage-efficient mapping of signals to the physical memories. The last phase of the methodology is an exploration approach for energy-aware banking of the on-chip memory, which takes into account both the static and dynamic energy consumption.

Scratch-pad memory banking for energy reduction in embedded signal processing systems

2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS), 2013

ABSTRACT Many signal processing systems, particularly in the multimedia and telecommunication dom... more ABSTRACT Many signal processing systems, particularly in the multimedia and telecommunication domains, are synthesized to execute data-intensive applications: their cost related aspects - namely power consumption, performance, and chip area - are heavily influenced, if not dominated, by the data transfer and storage aspects. In such applications, hierarchical memory organizations reduce energy consumption by exploiting the nonuniformity of memory accesses and assigning the frequentlyaccessed data to low levels of the hierarchy. Moreover, within a given level, power can be reduced by memory partitioning - whose principle is to divide the address space in several smaller blocks, and to map these blocks to physical memory banks. This paper addresses the problem of energy-aware banking of on-chip memories for data-intensive applications, proposing a technique that is guided by the intensity of memory accesses within the array space of signals.

Silicon microstrip detectors R and D at UB/EPPG and IMT Bucharest and collaboration with INFN Italy

Metrology measurements on a 64 cm long silicon microstrip detector

Beam test results on Si and GaAs microstrip detectors with length up to 64 cm

Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, 1995

Electron microstrip silicon detector for high flux density

Optimized polysilicon CMOS technology for gate array applications

1998 International Semiconductor Conference. CAS'98 Proceedings (Cat. No.98TH8351), 1998

The gate arrays option in manufacturing ASIC CMOS is conditioned by the possibility of satisfying... more The gate arrays option in manufacturing ASIC CMOS is conditioned by the possibility of satisfying small orders requirements of small- and medium-sized electronic equipment manufacturing companies, in a large variety of circuits. The authors present contributions in optimizing critical processes for an n-well CMOS polysilicon gate arrays technology. Technological achievements were proved by measurements on the test devices but mainly

Silicon microstrip dummy detectors:processing and dimensional measurements

MINERvA neutrino detector response measured with test beam data

Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, 2015

The MINERvA collaboration operated a scaled-down replica of the solid scintillator tracking and s... more The MINERvA collaboration operated a scaled-down replica of the solid scintillator tracking and sampling calorimeter regions of the MINERvA detector in a hadron test beam at the Fermilab Test Beam Facility. This article reports measurements with samples of protons, pions, and electrons from 0.35 to 2.0 GeV/c momentum. The calorimetric response to protons, pions, and electrons are obtained from these data. A measurement of the parameter in Birks' law and an estimate of the tracking efficiency are extracted from the proton sample. Overall the data are well described by a Geant4-based Monte Carlo simulation of the detector and particle interactions with agreements better than 4%, though some features of the data are not precisely modeled. These measurements are used to tune the MINERvA detector simulation and evaluate systematic uncertainties in support of the MINERvA neutrino cross section measurement program. Fermilab preprint FERMILAB-PUB-15-018-ND Keywords: hadron calorimetry, electromagnetic calorimetry, Birks' law, test beam PACS: 13.75.-n 13.75.Cs 07.20.Fw]

$Research paper thumbnail of Measurement of Muon Neutrino Quasielastic Scattering on a Hydrocarbon Target at E_{ν}∼3.5 GeV$

Measurement of Muon Neutrino Quasielastic Scattering on a Hydrocarbon Target at E_{ν}∼3.5 GeV

Physical Review Letters, 2013

We report a study of νµ charged-current quasi-elastic events in the segmented scintillator inner ... more We report a study of νµ charged-current quasi-elastic events in the segmented scintillator inner tracker of the MINERvA experiment running in the NuMI neutrino beam at Fermilab. The events were selected by requiring a µ − and low calorimetric recoil energy separated from the interaction vertex. We measure the flux-averaged differential cross-section, dσ/dQ 2 , and study the low energy particle content of the final state. Deviations are found between the measured dσ/dQ 2 and the expectations of a model of independent nucleons in a relativistic Fermi gas. We also observe an excess of energy near the vertex consistent with multiple protons in the final state.

Design, calibration, and performance of the MINERvA detector

Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, 2014

The MINERvA 1 experiment is designed to perform precision studies of neutrino-nucleus scattering ... more The MINERvA 1 experiment is designed to perform precision studies of neutrino-nucleus scattering using ν µ andν µ neutrinos incident at 1-20 GeV in the NuMI beam at Fermilab. This article presents a detailed description of the MINERvA detector and describes the ex situ and in situ techniques employed to characterize the detector and monitor its performance. The detector is comprised of a finely-segmented scintillator-based inner tracking region surrounded by electromagnetic and hadronic sampling calorimetry. The upstream portion of the detector includes planes of graphite, iron and lead interleaved between tracking planes to facilitate the study of nuclear effects in neutrino interactions.

Trapping in proton irradiated p+-n-n+silicon sensors at fluences anticipated at the HL-LHC outer tracker

Journal of Instrumentation, 2016

Radiation hardness studies of neutron irradiated CMOS sensors fabricated in the ams H18 high volt... more Radiation hardness studies of neutron irradiated CMOS sensors fabricated in the ams H18 high voltage process M. Fernández García, C. Gallrapp, M. Moll et al. Testbeam and laboratory characterization of CMS 3D pixel sensors M Bubna, D Bortoletto, E Alagoz et al. HVMUX, the High Voltage Multiplexing for the ATLAS Tracker Upgrade E Giulio Villani, P Phillips, J Matheson et al. Radiation damage effects in Si materials and detectors and rad-hard Si detectors for SLHC Z Li A X P : 1505.01824

Impact of low-dose electron irradiation on n+p silicon strip sensors

Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, 2015

ABSTRACT

Measurement of the mass difference m(Ds+)-m(D+) at CDF II

Physical Review D, 2003

We present a measurement of the mass difference m(D s ϩ )Ϫm(D ϩ ), where both the D s ϩ and D ϩ a... more We present a measurement of the mass difference m(D s ϩ )Ϫm(D ϩ ), where both the D s ϩ and D ϩ are reconstructed in the ϩ decay channel. This measurement uses 11.6 pb Ϫ1 of data collected by CDF II using the new displaced-track trigger. The mass difference is found to be m(D s ϩ )Ϫm(D ϩ )ϭ99.41Ϯ0.38(stat) Ϯ0.21(syst) MeV/c 2 .