seema narwal

Unified intercept probability analysis of multi-user multi-relay aided decode-and-forward wireless systems

International journal of information technology, Mar 11, 2024

Investigation of RF and linearity performance of electrode work‐function engineered HDB vertical TFET

Micro & Nano Letters, 2019

This work realises a hetero-dielectric buried oxide vertical tunnel field effect transistor (HDB ... more This work realises a hetero-dielectric buried oxide vertical tunnel field effect transistor (HDB VTFET) and investigates its radio frequency (RF) and linearity characteristics. First time, the concept of hetero-dielectric buried oxide (BOX) in VTFET is used to obtain the superior improvement in terms of different RF and linearity figure of merits such as C gs , C gd , C gg , f T , Gain Bandwidth Product (GBP), t, Transconductance Frequency Product (TFP), Transconductance Generation Factor (TGF), g m2 , g m3 , VIP 2 , VIP 3 , IIP 3 , IMD 3 and 1-dB compression point. Also, the influence of HfO 2 BOX length scaling on these FOMs is analysed. The results reveal that the HDB VTFET can be a promising contender to replace bulk metal-oxide semiconductor field-effect transistors in analogue/mixed signal system-on-chip and high-frequency microwave applications and the accuracy of this device is validated by TCAD Sentaurus simulator.

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Performance investigation of electrode work‐function engineered hetero‐dielectric buried oxide vertical TFET

IET circuits, devices & systems, Oct 1, 2019

For enhancement of I ON and I OFF in tunnel field-effect transistors (TFETs), it is important to ... more For enhancement of I ON and I OFF in tunnel field-effect transistors (TFETs), it is important to choose novel materials and structures. Here, the authors design a hetero-dielectric buried oxide vertical TFET (HDB VTFET) and its device characteristics has been investigated. This proposed device reveals the tremendous improvement in terms of sub-threshold slope, drain-induced barrier lowering, on-current and suppresses the ambipolar behaviour up to V gs = −1.0 V by maintaining very low off-current. Hence, the concept of hetero-dielectric buried oxide (BOX) and two metal electrodes having different work-functions are used here to obtain better results in terms of the current driving capability, steep subthreshold slope (SS) and drain-induced barrier lowering (DIBL). This device is a promising candidate for low-power consumption applications.

Comparison of Single Bit 14 T and 8 T Full Adder for Low-Power VLSI Design

This paper presents a new design for 14 transistor single bit full adder, implemented using five ... more This paper presents a new design for 14 transistor single bit full adder, implemented using five transistor XNOR/XOR cell and transmission gate multiplexer. For transmission gate multiplexer complementary gate control signals are required and in 14 transistor full Adder both XOR and XNOR signals are generated. XNOR/XOR cell shows high power consumption than single XNOR gate. So, 8 transistor full adder has been designed using 3 transistor XNOR gate and comparison is made between 14 T and 8 T full adder. Simulation has been done using 0.35μm technology. These circuits were redesigned at the transistor-level in tsmc 0.18μm technology and comparison reported here uses Mentor Graphics ELDO simulations to assess their performance. Circuit works well with reduced supply voltage and simulations have been carried out up to 1.8V supply voltage. 8T full adder shows better performance in terms of power consumption and transistor count as compared to 14 T full adder.

Investigation of RF and linearity performance of electrode work‐function engineered HDB vertical TFET

Micro & Nano Letters, 2018

This work realises a hetero-dielectric buried oxide vertical tunnel field effect transistor (HDB ... more This work realises a hetero-dielectric buried oxide vertical tunnel field effect transistor (HDB VTFET) and investigates its radio frequency (RF) and linearity characteristics. First time, the concept of hetero-dielectric buried oxide (BOX) in VTFET is used to obtain the superior improvement in terms of different RF and linearity figure of merits such as C gs , C gd , C gg , f T , Gain Bandwidth Product (GBP), t, Transconductance Frequency Product (TFP), Transconductance Generation Factor (TGF), g m2 , g m3 , VIP 2 , VIP 3 , IIP 3 , IMD 3 and 1-dB compression point. Also, the influence of HfO 2 BOX length scaling on these FOMs is analysed. The results reveal that the HDB VTFET can be a promising contender to replace bulk metal-oxide semiconductor field-effect transistors in analogue/mixed signal system-on-chip and high-frequency microwave applications and the accuracy of this device is validated by TCAD Sentaurus simulator.

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Performance investigation of electrode work‐function engineered hetero‐dielectric buried oxide vertical TFET

IET Circuits, Devices & Systems, 2019

For enhancement of I ON and I OFF in tunnel field-effect transistors (TFETs), it is important to ... more For enhancement of I ON and I OFF in tunnel field-effect transistors (TFETs), it is important to choose novel materials and structures. Here, the authors design a hetero-dielectric buried oxide vertical TFET (HDB VTFET) and its device characteristics has been investigated. This proposed device reveals the tremendous improvement in terms of sub-threshold slope, drain-induced barrier lowering, on-current and suppresses the ambipolar behaviour up to V gs = −1.0 V by maintaining very low off-current. Hence, the concept of hetero-dielectric buried oxide (BOX) and two metal electrodes having different work-functions are used here to obtain better results in terms of the current driving capability, steep subthreshold slope (SS) and drain-induced barrier lowering (DIBL). This device is a promising candidate for low-power consumption applications.

FPGA based Hardware Implementation of Variant DPCM Image Compression Technique (Multiple LUT-DPCM)

International Journal of Applied Information Systems, 2014

This paper proposed FPGA implementation of variant DPCM based image compression technique (Multip... more This paper proposed FPGA implementation of variant DPCM based image compression technique (Multiple LUT-DPCM). Image compression addresses the problem of reducing the amount of data required to represent a digital image. Such data compression can be achieved by reducing the redundancies of the image data in order to be able to store or transmit data in an efficient form. There are various onboard data compression techniques used in image processing. Out of which DPCM based compression technique is the most commonly used one. For the hardware implementation, an algorithm for Multiple LUT DPCM is designed. VHDL code is developed based on the algorithm designed. After simulation and verification of developed code with test data generated, it implemented in to hardware. The developed hardware's functionality, then verified with the already simulated data and also with real image data.

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