Ultraminiaturized Three-Dimensional IPAC Packages With 100 μm Thick Glass Substrates for Radio Frequency Front-End Modules
Journal of Electronic Packaging, Jul 27, 2017
This paper presents innovative compact three-dimensional integrated passive and active components... more This paper presents innovative compact three-dimensional integrated passive and active components (3D IPAC) packages with ultrathin glass substrates for radio frequency (RF) long-term evolution (LTE) front-end modules (FEMs). High component density was achieved through double-side integration of substrate-embedded passives for impedance matching networks and three-dimensional (3D) double-side assembly of filters onto glass substrates. Glass with 100 μm thickness formed the core of the package, while four build-up layers with 15 μm thickness each were used to embed passives and form redistribution layers (RDLs). Advanced panel-scale double-side assembly processes were developed with low-cost mass reflow. Board-level assembly was realized with paste-printed solder balls and reflow on printed circuit board (PCB) with no intermediate substrates. Electrical performance of filters with substrate-embedded impedance matching networks was characterized and compared to simulations.
New era in automotive electronics, a co-development by Georgia tech and its automotive partners
The new trends in automotive electronics such as autonomous driving, in-car infotainment, and all... more The new trends in automotive electronics such as autonomous driving, in-car infotainment, and all-electric cars, require an entirely different electronic vision and technologies than are pursued today for automotive industry. Georgia Tech proposes system scaling as a new frontier to address the upcoming era of automotive challenges. It also proposes an innovative 3D system package architecture taking into account electrical, mechanical and thermal designs as well as new digital, RF, sensors, radar millimeter-wave and power technologies. It proposes highly innovative large panel-based, ultra-thin glass packaging with many innovations in electrical, thermal, mechanical designs, materials, processes, wiring lithography, fine-pitch and high-throughput assembly and highly-conductive through-Cu vias for signal, power and heat transfer. Such an approach is proposed to lead to highly-functional sub-systems for integration of disparate set of technologies at lowest cost, in smallest ultra-miniaturized size with shortest interconnections with lowest power consumption.
High density electrical interconnections in liquid crystal polymer (LCP) substrates for retinal and neural prosthesis applications
Retinal prostheses implemented by means of electrical stimulation of retinal ganglion cells have ... more Retinal prostheses implemented by means of electrical stimulation of retinal ganglion cells have been previously demonstrated with 16 and 60 channel microstimulator arrays. Blind patients with severe retinal degeneration (e.g., retinitis pigmentosa (RP) have been able to use these devices to navigate and read large letters. However, to dramatically improve the effectiveness of such prostheses, and to enable a variety
Low-cost and low-loss 3D silicon interposer for high bandwidth logic-to-memory interconnections without TSV in the logic IC
This paper presents the design, fabrication and electrical characterization of a low loss and low... more This paper presents the design, fabrication and electrical characterization of a low loss and low cost non-traditional silicon interposer, demonstrating the high bandwidth chip-to-chip interconnection capability of the 3D silicon interposer, with equivalent or better performance than 3D ICs with TSVs, at a much lower cost. This scalable approach uses thin polycrystalline silicon in wafer or panel form, forms lower cost through-package-vias (TPVs) at fine pitch by special high throughput laser processes. The electrical performance is improved by thick polymer liners within the TPVs. Double side package processes for TPV metallization and RDL layers using dry film polymers and plating leads to significant cost reduction compared to single side TSV and BEOL wafer processes. Combined loss of 3mm long CPW lines and two TPVs in the low loss silicon interposer was demonstrated at less than 1dB at 10GHz. The fine pitch TPV capability and low loss of this non-traditional silicon interposer leads to 3D interposers with double side chips interconnected at equivalent bandwidth to wide bus I/O 3D ICs at a much lower cost and with better testability, thermal management and scalability.
Industry consortium for new era of automotive electronics with entire system-on-package vision at Georgia Tech
European Microelectronics and Packaging Conference, Sep 1, 2015
The new trends in automotive electronics such as autonomous driving, in-car smartphone-like infot... more The new trends in automotive electronics such as autonomous driving, in-car smartphone-like infotainment, privacy and security, and all electric cars, require an entirely different vision than is pursued today. Georgia Tech sees unprecedented challenges and opportunities to address these needs because of disparate set of technologies that hitherto fore thought to be impossible to integrate. It proposes a systematic approach to system scaling, heterogeneous integration and innovative package architectures as the new era in electronics hardware with particular focus in electrical, mechanical and thermal designs and new digital, RF, sensors, millimeter wave and power technologies. The Georgia Tech team proposes a transformative and yet a strategic approach to automotive electronics, called System Scaling, leading to entire automotive system-on-a package. Such a system must integrate many disparate technologies such as high speed digital, optical, RF and wireless sensing and data processing from 100s of sensors as well as ultrahigh power electronics. Georgia Tech proposes a highly innovative large panel-based, ultra-thin glass packaging in 3D double-side architecture with many, many innovations in designs, materials, processes, wiring lithography, fine-pitch and highly conductive through-vias for thermal management and system integration. Such an approach is proposed to lead to highly-functional systems with disparate set of technologies at lowest cost, in smallest ultra-miniaturized size with shortest interconnections with lowest power consumption. Georgia Tech views this approach to be superior to current approaches such as chip-first or wafer fanout or chip-last organic, leadframe and molded packaging technologies.
Conformal Atomic Layer Deposition (ALD) of alumina on high surface-area porous copper electrodes to achieve ultra-high capacitance density on silicon interposers
Abstract This paper describes an innovative approach to achieve higher capacitance density on sil... more Abstract This paper describes an innovative approach to achieve higher capacitance density on silicon interposers than what has been reported with trench capacitors. The approach consists of a novel silicon-compatible low-temperature sinterable metal particulate electrode and a ...
Ultra-Precise Low-Cost Surface Planarization Process for Advanced Packaging Fabrications and Die Assembly: A Survey of Recent Investigations on Unit Process Applications and Integrations
A suite of highly precise surface planarization equipment and associated unit process have been d... more A suite of highly precise surface planarization equipment and associated unit process have been developed for several years. Recent studies showed that this process is suitable to address the persistent needs for improved planarity of surface topographies and bonding interfaces during advanced packaging fabrications and assembly. Myriad process capabilities have been achieved to date on both wafer-level for device die fabrications as well as on panel-level for interposer and substrate fabrications. Some planarization highlights include (i) achieving copper pillars height uniformity of less than 1.5um across entire 300mm Si low-k wafer area, (ii) being able to integrate with panel-, lamination-based RDL fabrications based on either pohto-lithography method or by direct laser patterning methods in planarizing both patterned plating features and blanket overburden layer structure, and (iii) establishing the manufacturing readiness for large panel substrate sizes.
An Advanced Photosensitive Dielectric Material for High-Density RDL with Ultra-Small Photo-Vias and Ultra-Fine Line/Space in 2.5D Interposers and Fan-Out Packages
In this paper, we introduce an advanced photosensitive dielectric material (PDM) we recently deve... more In this paper, we introduce an advanced photosensitive dielectric material (PDM) we recently developed to realize a high resolution and low coefficient thermal expansion (CTE) for next-generation high-density re-distribution layer (RDL) for 2.5D interposer and high-density fan-out package applications. For high-density RDL, photosensitive materials need to have (1) a high resolution, (2) high insulation reliability and (3) semi-additive process (SAP) compatibility. We have developed an advanced photosensitive dielectric material witch meets these three requirements. We demonstrate ultra-small via (3 um) by i-line stepper. For SAP compatibility, we have fabricated copper traces of 2um lines and spaces on the PDM by using SAP with sputtered Ti/Cu seed layer. The insulation reliability test was performed at the condition of Bias-Highly Accelerated-Stress Test, 135 deg.C. 85% R.H. on test coupon with 5um thick PDM. As a result, over 300 hours insulation reliability was confirmed. These results mean that the newly-developed PDM is suitable for next generation 2.5D interposer and high-density fan-out package applications. In terms of a package reliability, a low CTE and low process temperature are desired. In order to reduce the CTE of the material and maintain high resolution, nano-size fillers were integrated into the material. As a result, CTE of 30-35 ppm / deg.C was achieved. Curing temperature of the PDM is designed at 180 deg.C which is lower than most of the advanced dielectric materials. These two features contribute to reduce warpage of high density substrates and interposers, so it is expected to be applied to multiple layer application. We also fabricated test coupon with daisy chain structure connected by ultra-small vias and very stable via resistance was confirmed. In conclusion, our newly-developed PDM is a promising dielectric material for highly reliable high-density redistribution layer (RDL) for 2.5D interposers and fan-out package applications.
Materials, processes and reliability of mixed-signal substrates for SOP technology
Saketh Mahalingam*#, Shashikant Hegde*', Jamie Ahmad*#, Raghuram V. Pucha*#, Venky Sunda... more Saketh Mahalingam*#, Shashikant Hegde*', Jamie Ahmad*#, Raghuram V. Pucha*#, Venky Sundaram', Fuhan Liu', George White', Rao Tummala' and Suresh K. Sitaraman*' 'Packaging Research Center * Computer-Aided Simulation of Packaging Reliability (CASPaR) Lab
Double-sided 3D glass interposers and packages, with through package vias (TPV) at the same pitch... more Double-sided 3D glass interposers and packages, with through package vias (TPV) at the same pitch as TSVs in Si, have been proposed to achieve high bandwidth between logic and memory with benefits in cost, process complexity, testability and thermal over 3D IC stacks with TSV. However, such a 3D interposer introduces power distribution network (PDN) challenges due to increased power delivery path length and plane resonances. This paper investigates the use of coaxial through-package-vias (TPVs) with high dielectric constant liners as an effective method to deliver clean power within a 3D glass package, and provides design and fabrication guidelines to achieve the PDN target impedance. The Coaxial TPV structure is simulated using electromagnetic (EM) solvers and a simplified equivalent circuit model to study via impedance and parasitics. Test vehicles with anodized tantalum oxide capacitors were fabricated in ultra-thin, 100µm thick glass interposers to demonstrate process feasibility, with a capacitance density of 5 nF/mm 2. Self-impedance (Z11) of a 3D glass interposer containing the coaxial TPVs was analyzed with variations in (a) Via location, (b) Number of coaxial vias, and (c) Via capacitance and stack-up, to provide optimal PDN design guidelines. Based on the above parameters, the added decoupling vias achieved more than 30% impedance suppression over multiple resonance frequencies between 0.5-6 GHz, providing an effective and flexible PDN design method for double-side 3D glass interposers.
Thin polymer dry-film dielectric material and a process for 10 um interlayer vias in high density organic and glass interposers
This paper describes the first demonstration of 10 μm diameter interlayer vias in low-moisture up... more This paper describes the first demonstration of 10 μm diameter interlayer vias in low-moisture uptake and low surface-roughness dry film polymer dielectric for multi-layered re-distribution layer (RDL) structures to achieve 50 μm bump pitch in high density organic and glass interposers. A new series of polymer dry films, ZS-100, at 10 μm thickness were deposited on thin and low CTE organic or glass cores using double-sided vacuum lamination processes. The ultra-small vias were fabricated by 248nm KrF excimer laser drilling, followed by electroless and electrolytic copper plating. Fully-filled via structures were successfully fabricated without any chemical-mechanical polishing. The processes demonstrated in this paper achieve much finer bump pitch than current organic packages, and can be scaled to large panels leading to lower cost than previous work in fine pitch Si interposers using back-end of line (BEOL) wafer processes.
CPW High Q Inductors on Organic Substrates Sidharth Dalmia, Seock Hee Lee, Venky Sundaram, Sung H... more CPW High Q Inductors on Organic Substrates Sidharth Dalmia, Seock Hee Lee, Venky Sundaram, Sung Hwan Min, Madhavan Swaminathan* and Rao ... TEM approximations as explained in [2]. A 2D electromagnetic solver such as ANSOFT 2D provides R, L, G, C matrices, for ...
Ultra-fine photoresist image formation for next generation high-density PWB substrate
The International journal of microcircuits and electronic packaging, 2000
Fuhan Liu*, Venky Sundaram, George White, and Rao R.Tummala Packaging Research Center Georgia Ins... more Fuhan Liu*, Venky Sundaram, George White, and Rao R.Tummala Packaging Research Center Georgia Institute of Technology 813 Ferst Drive Atlanta, Georgia 30332 Phone: 404-385-0731, 404-894-9394, 404-894-0514, and 404-894-9097 Fax: 404-894-3842 ...
IEEE Transactions on Electromagnetic Compatibility, Jun 1, 2017
In this paper, we propose glass interposer electromagnetic bandgap (EBG) structure to efficiently... more In this paper, we propose glass interposer electromagnetic bandgap (EBG) structure to efficiently suppress power/ground noise coupling. We designed, fabricated, measured, and analyzed a glass interposer EBG structure for the first time. Glass interposer EBG structure test vehicles were fabricated using a thin-glass substrate, low-loss polymer layers, and periodic metal patches with through glass vias (TGVs) in glass interposer power distribution network. Using the dispersion characteristics, we thoroughly analyzed and derived f L and f U of the glass interposer EBG structure. We experimentally verified that the proposed glass interposer EBG structure achieved power/ground noise suppression (below-40 dB) between f L of 5.8 GHz and f U of 9.6 GHz. Derived f L and f U based on dispersion analysis, full three-dimensional electromagnetic (3-D-EM) simulation and measurement achieved good correlation. In the glass interposer EBG structure, tapered structure of the TGV and thickness of the low-loss polymer used for metal-layers lamination affected the noise suppression bandgap significantly. The effectiveness of the proposed glass interposer EBG structure on suppression of the power/ground noise propagation and coupling to high-speed TGV channel was verified with 3-D-EM simulation. As a result, the proposed glass interposer EBG structure successfully and efficiently suppressed the power/ground noise propagation and improved eye-diagram of the high-speed TGV channel. Index Terms-Electromagnetic bandgap (EBG), glass, interposer, measurement, power/ground noise coupling, suppression, through glass via (TGV).
A new approach to power integrity with thinfilm capacitors in 3D IPAC functional module
ABSTRACT This paper presents a new active and passive integration concept called 3D IPAC (Integra... more ABSTRACT This paper presents a new active and passive integration concept called 3D IPAC (Integrated Actives and Passives) to address the power integrity in high-performance and multifunctional systems. The 3D IPAC consists of an ultra-thin glass module with through-vias and double-side integration of ultra-thin active and passive components to form functional modules. By integrating power ICs, storage capacitors and inductors, and high-frequency decoupling capacitors in ultra-thin (30-100 μm) glass substrates, 3D IPAC Voltage Regulator Module (3D IPAC VRM) provides a complete and ultra-miniaturized solution to power integrity. The ultra-thin 3D IPAC allows both actives and passives very close to each other and to the other active dies, resulting in improved performance over conventional SMDs and state-of-art IPDs for decoupling functions. The first part of the paper presents modeling results to show the benefits of the 3D IPAC module as a power integrity solution. The second part of the paper presents the fabrication and characterization of high-k thinfilm capacitors and etched aluminum film capacitors integrated on either sides of a through-via 3D IPAC glass substrate. This paper, therefore, demonstrates the integration of heterogeneous capacitors on a single ultra-thin glass substrate for the first time, and presents its benefits as a complete solution for power integrity.
IEEE Transactions on Components, Packaging and Manufacturing Technology, May 1, 2016
This paper proposes a wideband scalable circuit model for tapered through-package vias (TPVs) in ... more This paper proposes a wideband scalable circuit model for tapered through-package vias (TPVs) in glass interposers. By slicing TPVs horizontally into infinitesimally thin pieces and integrating along TPVs, an analytical solution was derived for the parasitic resistance (R), while semianalytical expressions were derived for the parasitic inductance (L), capacitance (C), and conductance (G) in the proposed model. Then, this model was verified against a 3-D electromagnetic solver in terms of S-parameters for various TPV dimensions, with the differences of S 21 magnitude and S 21 phases being less than 0.01 dB and 1°, respectively. In addition, two dual-via chains of different lengths were designed, fabricated, and measured to benchmark the proposed model up to 20 GHz. The excellent consistency between them further proves the validity of the proposed model. Finally, the effect of the TPV taper was comprehensively studied on the RLCG parameters. It was found that the TPV taper was beneficial to reduce the parasitic capacitance and conductance by as much as 40%. Despite these benefits, tapered TPVs are not preferred, because the parasitic resistance and inductance are the dominant factors for TPVs in glass, and the TPV taper increases the parasitic resistance drastically and also increases the parasitic inductance by as much as 80%.
IEEE Transactions on Components, Packaging and Manufacturing Technology, May 1, 2017
Glass substrates are emerging as a key alternative to silicon and conventional organic substrates... more Glass substrates are emerging as a key alternative to silicon and conventional organic substrates for high-density and high-performance systems due to their outstanding dimensional stability, enabling sub-5-µm lithographic design rules, excellent electrical performance, and unique mechanical properties, key in achieving board-level reliability at body sizes larger than 15 × 15 mm 2. This paper describes the first demonstration of the board-level reliability of such large, ultrathin glass ball grid array (BGA) packages directly mounted onto a system board, considering both their thermal cycling and drop-test performances. To investigate board-level reliability, glass BGA packages, 18.5 × 18.5 mm 2 in body size and 100 µm in thickness, were first designed and fabricated with a daisy-chain pattern. The glass test vehicles were fabricated at panel level, and then BGA balled by ball drop process with SAC105 solder balls, 250 µm in diameter at 400-µm pitch. After singulation, the glass packages were mounted onto printed circuit boards using standard surface mount technology assembly processes, and then subjected to reliability testing through thermal cycling and drop tests following JEDEC reliability standards. The effect of the coefficient of thermal expansion (CTE) of glass was evaluated by investigating low-and high-CTE glass substrates, with the CTEs of 3.8 and 9.8 ppm/°C, respectively. While all glass packages passed 1000 thermal cycles at −40/125°C as predicted by thermomechanical modeling using the Engelmaier-Wild model, the fatigue life of high-CTE samples exceeded 5000 thermal cycles. In addition, 28/30 drop-test samples passed the required 40 and 200 drops on corner and inner circuits, respectively, with no clear effect of the glass CTE. The predominant failure modes were systematically identified for both reliability tests.
Design and fabrication of bandpass filters in glass interposer with through-package-vias (TPV)
Abstract This paper presents the integration of WLAN (2.4 and 5GHz) bandpass filters in glass int... more Abstract This paper presents the integration of WLAN (2.4 and 5GHz) bandpass filters in glass interposer using through-package vias. The filters include novel embedded passive components such as stitched capacitors with reduced shunt parasitics and via-based inductors that ...
Uploads
Papers by Venky Sundaram