Tilman Kolks

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Architecture de simulation

L'invention concerne un simulateur convenant, en particulier, pour la simulation du comportem... more L'invention concerne un simulateur convenant, en particulier, pour la simulation du comportement equipement/logiciel de systemes encastres. L'architecture du simulateur permet aux systemes d'equipement/ logiciel d'etre realises sous forme de modules (15) de comportements caracteristiques bien determines. Une syntaxe de definition de module concise est utilisee pour decrire des comportements de modules, et un traducteur (150) fonctionne sur le module pour resumer des operations de comportements de modules a un niveau ne necessitant pas d'interaction directe a base de cycle de chaque module avec le moteur de simulation sous-jacent.

Control resynthesis for control-dominated asynchronous designs

Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems

Syntax directed translation based compilation from high-level concurrent programs has matured sig... more Syntax directed translation based compilation from high-level concurrent programs has matured significantly over the past few years. They have been applied to significant designs in the domains of digital signal processing and microprocessor designs. For data-path dominated designs, like those found in digital signal processing applications, syntax directed translation approaches have been shown to generate efficient asynchronous implementations. However for

Sizing of communication buffers for communicating signal processes

Proceedings of IEEE Workshop on VLSI Signal Processing

A method is presented for the minimal sizing of communication buffers in an environment of commun... more A method is presented for the minimal sizing of communication buffers in an environment of communicating signal processes. Existing methods based upon lifetime analysis techniques are mainly suited for sizing buffers in a network of processes with non-conditional interactions. The authors consider a more general problem where the execution of each process depends inherently on complex interactions with other processes as well as on its internal conditional behavior. To address the buffer sizing for this general case, the use of implicit state enumeration techniques is proposed. A dynamic data flow graph (DDF) is used as the model to describe the entire system of communicating processes. This DDF is translated into a network of finite state machine that forms state space on which methods based on implicit state space exploration are applied. To reduce the size of the state space, abstraction techniques are used to produce a simplified version in which irrelevant information is removed. The feasibility of the proposed approach is demonstrated by a practical signal processing example.<<ETX>>

Sizing and verification of communication buffers for communicating processes

Proceedings of 1993 International Conference on Computer Aided Design (ICCAD)

In this paper, a method is presented for minimal sizing and verification of communication buffers... more In this paper, a method is presented for minimal sizing and verification of communication buffers in an environment of communicating concurrent processes. Methods described in literature based upon lifetime analysis techniques are mainly suited for sizing butTers in a network of processes with non-conditional interactions. We consider a more general problem where the execution of each process inherently depends on complex interactwns with other processes aa well as ita internal conditwnal behavior and propose the use of implicit state enurneratwn techniques to solve buffer sizing and verification for this case. A model of the network of processes and buffers is introduced that is transformed into a network of finite state machines by modeling communicating buffers as counters. The transformed network forms a finite state space model on which implicit state space exploration algorithms are applied. The model allows us to handle the buffer sizing and verification problems with processes that operate on differen~but related clocks. To reduce the complexity of the state space, abstraction techniques can be used to produce simplified veraions of finite state machines that hide away unnecessarily detailed information. The feasibility of the proposed approach is demonstrated by a practical example.

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Hierarchical Optimization of Asynchronous Circuits

32nd Design Automation Conference, 1995

Many asynchronous designs are naturally specified and implemented hierarchically as an interconne... more Many asynchronous designs are naturally specified and implemented hierarchically as an interconnection of separate asynchronous modules that operate concurrently and communicate with each other. This paper is concerned with the problem of synthesizing such hierarchically defined systems. When the individual components are synthesized and implemented separately, it is desirable to take into account the degrees of freedom that arise from the interactions with the other components and from the specification. Specifically, we consider how one can find the set of implementations that can be "correctly substituted" for a component in the system while preserving the behavior of the total system. The notion of correct substitution is formally defined for a hierarchical network of possibly non-deterministic modules and a new solution framework based on trace theory is presented to compute and represent this complete set of correct substitutions. We show that the complete set can be captured by a single trace structure using the notion of a "maximal trace structure". We indicate how asynchronous synthesis methods may be applied to explore the solution space e.g. to generate a delay-insensitive implementation.

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Modeling and optimization of hierarchical synchronous circuits

Proceedings the European Design and Test Conference. ED&TC 1995

Synchronous designs are often described and implemented hierarchically as a network of interactin... more Synchronous designs are often described and implemented hierarchically as a network of interacting finite state machines. When the individual components are synthesized and implemented separately, it is desirable to take into account the degrees of freedom that arise from the interactions with the other components and from the specification. Specifically, we consider the problem of finding the complete set of implementations that can be correctly substituted for a component in a system without changing the behavior of the total system. In this paper, a synchronous trace set model is proposed to tackle this problem. The unambiguous way in which this model describes synchronous behavior provides us with a general method to model interacting finite state machines. We show that a single synchronous trace set can be used to characterize all possible substitutions in a correct substitution problem. We give a necessary notion of progress that permits us to choose a correct one from this set, or to show that no solution exists. We pro vide results of an implicit implementation of our approach applied to benchmarks ranging from small to very large state machines. These results show the feasibility of the proposed methods.

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A time abstraction method for efficient verification of communicating systems

Proceedings of the 31st annual conference on Design automation conference - DAC '94, 1994

An important practical approach to automatic verification of finite state concurrent systems is t... more An important practical approach to automatic verification of finite state concurrent systems is temporal logic model checking. However, a major barrier towards wider application of such methods is the state explosion problem that often occurs during the composition of complex communicating systems. In addition to being large, many systems have very deep state spaces as well. In this paper, we propose an abstraction method based on time abstraction which can significantly reduce both the size as well as the depth of the state space that must be explored during model checking. It is especially suited for applications involving systems that are loosely coupled in the sense that communication activity is relatively sparse, such as applications involving DSPs, which have large intervals of autonomous processing, with communication activity in between. All properties expressible with the temporal logic CTL or CTL-X are strongly preserved under the proposed abstraction. In particular, we give a method that can replace a chain of states by a single state with a time label. The abstracted model is represented by means of a timed label transition system model. We give a composition algorithm for composing the individually time abstracted models to form a global model that can be converted back to a conventional, but potentially much reduced,state space suitable for model checking. Furthermore, a similar approach can be followed in dealing with wait states in which a system is idling while waiting for an escape signal. For many cases, our approach is successful in alleviating the state explosion problem that often arises in composition of communicating systems.

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