Papers by Sung-Mo Steve Kang
Issues in the modeling of fiber optic systems
Computer aided design (CAD) tools prepare for an expanded role in the design of fiber-optical sys... more Computer aided design (CAD) tools prepare for an expanded role in the design of fiber-optical systems for high-performance computing and communications systems. One crucial part of the design of CAD tools is the efficient modeling of the optoelectronic components and the accurate prediction of the optical pulse deterioration along the optical link. This paper discusses circuit- and system-level models issues for fiber-optic interconnects consisting of optical devices such as laser diodes, photoreceivers, optical fibers, and other optoelectronic devices
2006 International Conference on Communications, Circuits and Systems, 2006
Estimating node voltages in bipolar circuits using linear programming
Proceedings of ISCAS'95 - International Symposium on Circuits and Systems
This paper addresses the problem of estimating node voltages in bipolar circuits. The node estima... more This paper addresses the problem of estimating node voltages in bipolar circuits. The node estimation algorithm uses linear programming constraint equations derived from the circuit structure and a heuristic objective function
Fast approximation of the transient response of Lossy Transmision Line Trees
Proceedings of the 30th international on Design automation conference - DAC '93, 1993
Page 1. Fast Approximation of the Transient Response of Lossy Transmission Line 'Ikees* M. S... more Page 1. Fast Approximation of the Transient Response of Lossy Transmission Line 'Ikees* M. Sriram and SM Kang Department of Electrical and Computer Engineering Coordinated Science Laboratory and Beckman Institute University of Illinois, Urbana, IL 61801 ...
1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers
The program has been discussed and approved by:-At the sitting of the SEUA interdepartmental Chai... more The program has been discussed and approved by:-At the sitting of the SEUA interdepartmental Chair of "Microelectronic Circuits and Systems" acting on the basis of "SYNOPSYS ARMENIA" CJSC SG
Testable CMOS design for robust and logical testability of stuck-open/stuck-on faults
[1991] Proceedings of the 34th Midwest Symposium on Circuits and Systems
ABSTRACT
Modeling, simulation and layout synthesis for giga scale CMOS VLSI
Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems
Summary form only given, as follows. With continuing proliferation of CMOS technology, we are app... more Summary form only given, as follows. With continuing proliferation of CMOS technology, we are approaching the era of giga-scale VLSI integration with lower power requirement. It would not be surprising to any member of the VLSI community that the validity of many CAD models become obsolete in the deep submicron technology. Also, the required chip complexity increases faster than what designers can afford in even shorter design cycle time. In order to manage the design complexity and contain the increase in the design effort of VLSI chips, it is critically important to fully automate the layout of VLSI circuits in a manner the finished layout meets all the design objectives such as timing, area, reliability constraints with high yield. Here the author considers new MOS models for deep submicron technologies, fast and accurate simulation techniques for VLSI circuits, MOS reliability modeling and diagnosis, and timing-driven layout CMOS synthesis techniques. FPGA, standard cells based design and full custom design cases are considered. For FPGA, timing-driven partitioning is considered along with new CAD tool development trends. For standard cells based design, gate sizing techniques for meeting timing and low-power constraints with minimum area are discussed. For full custom design, an integrated environment for compact layout platforms, triple metal routing techniques and transistor sizing algorithms is discussed
Fast MOS circuit simulation with a direct equation solver
ABSTRACT
A high-speed integrated optoelectronic photoreceiver
[Proceedings] 1992 IEEE International Symposium on Circuits and Systems
ABSTRACT
A Convex Programming Approach to Transistor Sizing
Design Automation for Timing-Driven Layout Synthesis, 1993
ABSTRACT
Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit
We present a hierarchical multilevel VHDL simulator for large systems described at the transistor... more We present a hierarchical multilevel VHDL simulator for large systems described at the transistor, gate and higher levels. We exploit the hierarchy and regularity in VHDL descriptions to reduce the memory requirements drastically. The simulation algorithm handles MOS digital designs with bidirectional signal flow. We have augmented VHDL descriptions with signal strengths and timing; and also proposed a method to extend VHDL to accept transistor-level descriptions. Simulation results are provided for s a mple VHDL circuits.
SCS 2003. International Symposium on Signals, Circuits and Systems. Proceedings (Cat. No.03EX720), 2004
Domino keeper has to be upsized to keep the noise margin in high fan-in dynamic gates, which incr... more Domino keeper has to be upsized to keep the noise margin in high fan-in dynamic gates, which increases the power consumption and slows down the evaluation. We propose a four-phase non-full swing keeper design to solve this dilemma. Non-full swing switching at the keeper gate together with alleviated contention help to reduce power consumption and delay. Simulation of 16-input OR gate using 0.13um CMOS SPICE parameters shows that proposed keeper design can reduce power consumption and delay by 26% and 24%, respectively.
Modeling and simulation of metal-semiconductor-metal photodetector using VHDL-AMS
2004 IEEE International Conference on Cluster Computing (IEEE Cat. No.04EX935)
1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)
In this paper, we present a new approach to the problem of inverter elimination in domino logic s... more In this paper, we present a new approach to the problem of inverter elimination in domino logic synthesis. A small piece of static CMOS logic is introduced to the circuit to avoid significant area penalty resulting from duplication. To maximize the domino logic part and to minimize the static CMOS logic part, a generalized ATPG based logic transformation is proposed to eliminate or relocate a target inverter. Based on the new concept of dominating set of mandatory assignment (DSMA) and the corresponding implication graph, we propose algorithms to identify a minimum candidate set for a target inverter. Experimental results show that logic transformation based on implication graph can reduce transistor counts by 25% and power delay product by 25% on average.
IEE Proceedings J Optoelectronics, 1992
The authors have developed a set of equivalent circuit models for optical logic gates based on th... more The authors have developed a set of equivalent circuit models for optical logic gates based on the saturable gain and saturable absorption phenemona, and have implemented them on the iSMILE circuit simulator. These models have been created with a highly modular design to facilitate the construction of complex logic functions. Several design issues, such as logic threshold and switching speed, have been addressed. Models for the AND, OR, NAND, NOR and NOT gates, are presented, as well as detailed simulation results.
High-level hot carrier reliability-driven synthesis using macro-models
Proceedings of the IEEE 1995 Custom Integrated Circuits Conference, 1995
We present a systematic method to incorporate hot carrier reliability issues in high-level design... more We present a systematic method to incorporate hot carrier reliability issues in high-level design automation. This method attempts to iteratively redesign the given high-level circuit to achieve better long-term reliability using macro-models of standard circuit elements. A reliability simulation tool, ILLIADS-R, is used to develop those macro-models. The method has been applied to various high-level sequential circuits. The results show
Programmable High Speed Multi-Level Simultaneous Bidirectional I/O
8th International Symposium on Quality Electronic Design (ISQED'07), 2007
Abstract This paper describes a programmable high speed multi-level simultaneous bidirectional I/... more Abstract This paper describes a programmable high speed multi-level simultaneous bidirectional I/O. With programmable high speed differential current switching, the static current flow becomes dependent upon the number of bits in the outgoing data, from 0-bit ...
<title>Optimal design of leak-proof SRAM cell using MCDM method</title>
VLSI Circuits and Systems, 2003
ABSTRACT As deep-submicron CMOS technology advances, on-chip cache has become a bottleneck on mic... more ABSTRACT As deep-submicron CMOS technology advances, on-chip cache has become a bottleneck on microprocessor&#39;s performance. Meanwhile, it also occupies a big percentage of processor area and consumes large power. Speed, power and area of SRAM are mutually contradicting, and not easy to be met simultaneously. Many existent leakage suppression techniques have been proposed, but they limit the circuit&#39;s performance. We apply a Multi-Criteria Decision Making strategy to perform a minimum delay-power-area optimization on SRAM circuit under some certain constraints. Based on an integrated device and circuit-level approach, we search for a process that yields a targeted composite performance. In consideration of the huge amount of simulation workload involved in the optimal design-seeking process, most of this process is automated to facilitate our goal-pursuant. With varying emphasis put on delay, power or area, different optimal SRAM designs are derived and a gate-oxide thickness scaling limit is projected. The result seems to indicate that a better composite performance could be achieved under a thinner oxide thickness. Under the derived optimal oxide thickness, the static leakage power consumption contributes less than 1% in the total power dissipation.
We propose an efficient data path synthesis algorithm which generates bit-sliced layouts. Since d... more We propose an efficient data path synthesis algorithm which generates bit-sliced layouts. Since data path circuits have special characteristics which are different from those of random logic circuits, the dedicated synthesis system is required for efficient layouts. Our main goal in the data path synthesis is to satisfy the timing constraints of circuits as well as to reduce layout areas. Timing-driven placement and over-the-cell routing techniques are developed to generate data path modules. Also, signal interfaces between bit-slices are carefully considered to further reduce layout areas. Our synthesis techniques take advantage of the common characteristics of data path structures under timing constraints and applies mixed integer linear programming approach to solve the problem. The superior results from our data path synthesis system are demonstrated through comparison with the layout results with the simulated annealing technique.
A comprehensive circuit-level model of vertical-cavity surface-emitting lasers
Journal of Lightwave Technology, 1999
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Papers by Sung-Mo Steve Kang