Papers by Sudipta Bhawmik
An integrated cad system for design of testable vlsi circuits
To tackle the current day testing complexity of VLS circuits Design For Testability (DFT) is beco... more To tackle the current day testing complexity of VLS circuits Design For Testability (DFT) is becoming more of a necessity. However VLSI designers are yet to accept DFT mainly due to lack of effective tools. Expert systems technology promises to be a useful means to present to the designer the gamut of DFT knowledge developed so far, primarily by test experts, in a more effective way. This thesis reports an original research carried out by the author to develop a knowledge based expert system (DFTEXPERT) which provides the designer with expert assistance in designing testable VLSI chips. The basic approach taken is to configure testable structures in a given RTL circuit description utilizing the available circuit resources (like registers) and reconfiguring them to DFT structures (Scan Paths and Linear Feedback Shift Registers) using the basic rules of DFT. A formal optimization technique has been proposed to control the chip area overhead resulting from the incorporation of DFT logi...
Built-In Self-Test and Test Scheduling for Interposer-Based 2.5D IC
ACM Transactions on Design Automation of Electronic Systems, 2015
Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems, Nov 1, 2006
In this paper, we explore two techniques, under the existing scan-based built-in self-test (BIST)... more In this paper, we explore two techniques, under the existing scan-based built-in self-test (BIST) architectures, for improving the test quality with practically no additional overhead. The proposed technique are an almost-full-scan BIST strategy and a general scan-based BIST test application scheme. We first demonstrate that under the scan-based BIST architecture, full scan may not result in the highest fault coverage (FC) and unscanning a small number of scan flip-flops may increase the BIST FC. We then present an algorithm for identifying those not-to-be-scanned flip-flops. We further show that the proposed general scan-based BIST test application scheme could also result in higher BIST FC and only requires a minor modification to the BIST controller. Experiments have been conducted using an industrial tool, psb2, on benchmark circuits to illustrate the effectiveness of the proposed techniques and algorithms. The results have demonstrated that both techniques are able to maximize the FC and reduce the test application time without additional test hardware comparing to the conventional scan-based BIST architectures.
Almost full-scan BIST method and system having higher fault coverage and shorter test application time
Enhanced controllability for IDDQ test sets using partial scan
28Th Acm Ieee Design Automation Conference, Feb 1, 1991
It has been shown recently that the advantages of Z~W testing for stuck-at faults are redueed tes... more It has been shown recently that the advantages of Z~W testing for stuck-at faults are redueed test set size, increased fault coverage and faster test generation time. Also untestability due to poor observability is eliminated. However, untestability due to poor controllability still remains and affects the Z~~Q test results. In this paper, we introduce the concept of partial scan in l~~Q test generation process. This results in increased eontrollability and hence reducing untestable faults in Z~~Q test results. Moreover, resulting test sets are further redueed and overall test generation time is improved.
System and Method of Testing Through-Silicon Vias of a Semiconductor Die
Method and apparatus for built-in self-test with multiple clock circuits
Method and system for improving the test quality for scan-based BIST using a general test application scheme
Method for implementing a bist scheme into integrated circuits for testing RTL controller-data paths in the integrated circuits
Test Controller for 3D Stacked Integrated Circuits
Scan Chain Access in 3D Stacked Integrated Circuits
Introduction to SystemC
Proceedings of the the 14th International Conference on Vlsi Design, Jan 3, 2001
Method and apparatus for partitioning long scan chains in scan based BIST architecture
KET—A Tool for Building Expert Systems
IETE Journal of Research, 1988
Automated Design For Testability (DFT) Tools for VLSI Circuits
IETE Journal of Research, 1988
Efficient characterisation of cellular automata
IEE Proceedings E Computers and Digital Techniques, 1990
... Rules 120 and 90 are illustrated in Fig. 2. The combinational logic equiva-lent for rule 120 ... more ... Rules 120 and 90 are illustrated in Fig. 2. The combinational logic equiva-lent for rule 120 is given as qi(t + 1) = qi+ l(t)4i-I(t) + qi+ l(t)Lii(t) + 4i+ l(t)qiqi-t (14 81 Page 2. The minimised expression for rule 90 is qi(t + 1) = qi+ l(t)Gi-+ 4i+ l(t)qi-= qi+l(t)@qi-l(t) (14 ...
PSBIST: A partial-scan based built-in self-test scheme
Proceedings of IEEE International Test Conference - (ITC), 1993
Partial-Scan based Built-In Self-Test (PSBIST) is a versa-tile Design for Testability (DFT) schem... more Partial-Scan based Built-In Self-Test (PSBIST) is a versa-tile Design for Testability (DFT) scheme, which employs pseudo-random BIST at all levels of test to achieve fault coverages greater than 98% on average, and supports de-terministic partial scan at the IC level to achieve ...
A practical method for selecting partial scan flip-flops for large circuits
Proceedings Tenth International Conference on VLSI Design, 1997
This paper describes a method of flip-flop selection (for BIST or Partial Scan) where the selecti... more This paper describes a method of flip-flop selection (for BIST or Partial Scan) where the selection process proceeds in a module by module basis. A complete circuit is assumed to be made up of different modules. The method uses the circuit graph of an individual module and uses the top level connectivity information in between modules to select flip-flops in that module. It then deletes the module from the top level graph, keeping only the combinational paths through that module to select flip-flops in the next module and so on until all modules are exhausted. The advantage of this process lies in the fact that partial scan or BIST can be inserted in a circuit on a module by module basis which is how circuits are designed usually. This means that test logic insertion need not wait for the availability of the complete circuit. This can reduce the turnaround time of a design. Also the redesign time after test logic insertion will go down as the design optimization can be carried out with the test logic already inserted. A number of experiments were conducted using different circuits which showed that the percentage of extra flip-flops selected by this method as opposed to selection over the global circuit, was quite small (around 3%). Also the processing time went down as the number of flip-flops increased
Core Based ASIC Design
VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design, 2000
A BIST scheme for the detection of path-delay faults
Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270), 1998
Path-delay faults represent a fault model that is commonly used to detect timing anomalies in a c... more Path-delay faults represent a fault model that is commonly used to detect timing anomalies in a circuit. Unlike stuck-at faults which can be detected using ATE at lower speed, test for path-delay faults require ATEs that can run at the clock frequency of the circuit under-test. However, with ever-increasing circuit-speed and complexity, ATEs are unable to keep up with this
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Papers by Sudipta Bhawmik