Pierre Gentil

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GIP-CNFM: a French education network moving from microelectronics to nanotechnologies CNFM: National coordination for education in microelectronics and nanotechnologies

Microelectronics high education in France is organized through a network composed of twelve cente... more Microelectronics high education in France is organized through a network composed of twelve centers, six of them having clean-rooms and technological facilities. During the year 2010, some activities moved from microelectronics to nanotechnologies in an effort to adapt our training facilities to the new nanoworld.

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Experimental investigation of ESD design window for fully depleted SOI N-MOSFETs

Microelectronic Engineering, 2011

In this article, the impact in FDSOI technology, of ground plane and buried oxide (BOX) size on t... more In this article, the impact in FDSOI technology, of ground plane and buried oxide (BOX) size on the robustness and on the NMOS triggering voltage (Vt1) is shown. We show experimentally that firstly thin BOX devices are more robust than thick BOX devices and secondly with a higher Vt1, thin BOX device purposes a larger range to trigger ESD network

Evidence of Radiation-Induced Dopant Neutralization in Partially-Depleted SOI NMOSFETs

IEEE Transactions on Nuclear Science, 2007

Radiation-induced dopant passivation is evidenced for the first time in partially-depleted SOI n-... more Radiation-induced dopant passivation is evidenced for the first time in partially-depleted SOI n-channel MOSFETs. Isochronal annealing experiments following 10 Mrad(SiO2) irradiation demonstrate that the neutralization of boron atoms in the NMOSFET body is most pronounced in the 125degC-150degC temperature range. This results in an abrupt decrease of the threshold voltage and the subthreshold swing, due to the transition of the

Correlation of Pseudo-MOS transistor and Hall effect measurements in thin SOI wafers

The carrier mobility in advanced SOI wafers was investigated by Pseudo-MOS transistor and Hall ef... more The carrier mobility in advanced SOI wafers was investigated by Pseudo-MOS transistor and Hall effect. Substrate biasing enables these measurements even when the Si film is fully depleted. The data indicate a good correlation between the two methods. Hall mobility is higher than the effective pseudo-MOSFET mobility as a result of prevailing phonon scattering.

Investigation of the Four-Gate Action in $hbox G^4$ -FETs

IEEE Transactions on Electron Devices, 2004

The Corbino Pseudo-MOSFET on SOI: Measurements, Model, and Applications

IEEE Transactions on Electron Devices, 2009

We propose the combination of magnetoresistance (MR) and Pseudo-MOSFET (Ψ-MOSFET) measurements as... more We propose the combination of magnetoresistance (MR) and Pseudo-MOSFET (Ψ-MOSFET) measurements as an improved method for the characterization of silicon-on-insulator (SOI) materials. Measurements were performed on ultrathin SOI Ψ-MOSFETs with Corbino geometry by applying high magnetic field and substrate biasing. Several models and extraction methods are developed and compared for an accurate evaluation of electron mobility. In particular, the series resistance effect is removed by using appropriate corrections. The MR mobility can be determined at low or variable electric field. The MR mobility behavior is investigated as a function of effective electric field, temperature, and film thickness. The correlation between the MR mobility and effective mobility, determined in Ψ-MOSFETs at zero magnetic field, enables a detailed analysis of the electron transport and scattering mechanisms in the silicon thin film.

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High-temperature performance of state-of-the-art triple-gate transistors

Microelectronics Reliability, 2007

High-temperature performance of state-of-the-art n-channel triple-gate transistors with 15 nm fin... more High-temperature performance of state-of-the-art n-channel triple-gate transistors with 15 nm fin-width, 60 nm fin-height, undoped body, high-k gate dielectric and metal gate is reported. The degradation of the on-current, transconductance and subthreshold swing, the shift in threshold voltage, the increase in gate/drain leakages and off-current with the temperature are analyzed up to 200°C. The comparison of short-and long-channel devices and the overall excellent performance at high temperature are outlined.

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Improved ESD protection in advanced FDSOI by using hybrid SOI/bulk Cointegration

We investigate the influence of different technological parameters on ESD robustness in advanced ... more We investigate the influence of different technological parameters on ESD robustness in advanced FDSOI devices. From Transmission Line Pulse (TLP) measurements, a comparison with other technologies enables us to evaluate the impact of ultrathin film and buried oxide. A solution based on hybrid SOI/bulk co-integration by using Silicon-On-Nothing technology is presented in order to improve ultra-thin film ESD performance.

A Two-Dimensional Model for Interface Coupling in Triple-Gate Transistors

IEEE Transactions on Electron Devices, 2007

The influence of the fin width on substrate-to-gate coupling in long-channel silicon-on-insulator... more The influence of the fin width on substrate-to-gate coupling in long-channel silicon-on-insulator triple-gate transistors is investigated. A complementary analysis, taking into account both the "front coupling" (variation of the front-channel threshold voltage V T 1 , as a function of the substrate bias V G2 ) and "back coupling" (variation of the back-channel threshold voltage V T 2 , as a function of the front-gate bias V G1 ) characteristics has been carried out. It is shown that the back coupling, as opposed to the front coupling, is highly sensitive to the fin width in narrowchannel devices and can even be used in fin width extraction.

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High quality Germanium-On-Insulator wafers with excellent hole mobility

Solid-state Electronics, 2007

... Fig. 3. Cross sectional TEM pictures of SiGe-On-Insulator substrates obtained by Ge condensat... more

Adaptation of the pseudo-MOS transistor for the characterization of silicon-on-sapphire films

Solid-state Electronics, 2000

The transport properties at the Si±Al 2 O 3 interface are probed directly on virgin silicon-on-sa... more The transport properties at the Si±Al 2 O 3 interface are probed directly on virgin silicon-on-sapphire (SOS) wafers. The measurement consists of the activation of the pseudo-MOS transistor, once the sapphire substrate has been aggressively thinned down to 30 lm. Typical transistor characteristics are measured and used to uncover the parameters that re¯ect the quality of SOS wafers: carrier mobility, density of interface traps, and residual doping. Ó

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Transport measurements in silicon-on-insulator films: Comparison of Hall effect, mobility spectrum, and pseudo-metal-oxide-semiconductor-field-effect-transistor techniques

Journal of Applied Physics, 2008

We report on the nature of electrical transport in silicon-on-insulator layers, investigated usin... more We report on the nature of electrical transport in silicon-on-insulator layers, investigated using several techniques: the standard single magnetic field Hall effect, mobility spectrum analysis of the magnetic field-dependent Hall effect, and the pseudo-metal-oxide-semiconductor-field-effecttransistor technique. For moderate and strong inversion, electrical transport in the temperature range 77-300 K is dominated by a lone electron species with a mobility of 500-1000 cm2/Vs. A good correlation is noted between these methods.

Influence of nitrogen or argon anneals on the properties of wafers and devices separated by implantation of oxygen

Journal of The Electrochemical Society, 1997

Wafers separated by implantation of oxygen (SIMOX) and annealed at high temperature in argon or n... more Wafers separated by implantation of oxygen (SIMOX) and annealed at high temperature in argon or nitrogen ambient are compared in terms of film, oxide, interface, and device properties. This evaluation is conducted by correlating pseudo-metal-oxide-semiconductor field effect transistor (Î¨-MOSFET) data in plain, unprocessed wafers with the performance of n- and p-channel transistors. In situ wafer characterization with the Î¨-MOSFET technique

Depletion-all-around in SOI G4-FETs: a conduction mechanism with high performance

Only in 4-gate SOI transistors (G4-FETs) can the channel be surrounded by depletion regions induc... more Only in 4-gate SOI transistors (G4-FETs) can the channel be surrounded by depletion regions induced by independent vertical MOS gates and lateral JFET gates. The majority carriers flow in the film volume, far from interfaces and junctions. We show that inversion layers, formed at the front and back interface, enable the junction gates to have enhanced control on the volume channel. High performance is experimentally demonstrated in terms of transconductance, subthreshold swing and gm/Id ratio. The basic mechanism, which involves a specific 2D gate coupling, is explained with a simple analytical model and simulations.

Analytical modeling of the two-dimensional potential distribution and threshold voltage of the SOI four-gate transistor

IEEE Transactions on Electron Devices, 2006

The two-dimensional (2-D) channel potential and threshold voltage of the silicon-on-insulator (SO... more The two-dimensional (2-D) channel potential and threshold voltage of the silicon-on-insulator (SOI) four-gate transistor (G 4 -FET) are modeled. The 2-D analytical body potential is derived by assuming a parabolic potential variation between the lateral junction-gates and by solving Poisson's equation. The model is used to obtain the surface threshold voltage of the G 4 -FET as a function of the lateral gate bias and for all possible charge conditions at the back interface. The body-potential model is extendable to fully depleted SOI MOSFETs and can serve to depict the charge-sharing and drain-induced barrier-lowering effects in short-channel devices. Index Terms-Charge sharing, drain-induced barrier lowering, four-gate transistor, junction FET (JFET), MOSFET, multiplegate transistor, potential distribution, short-channel effect, siliconon-insulator (SOI), threshold voltage, two-dimensional (2-D) modeling.

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A novel four-quadrant analog multiplier using SOI four-gate transistors (G4-FETs

A novel analog multiplier using SOI four-gate transistors (G4-FETs) is presented. Thanks to the m... more A novel analog multiplier using SOI four-gate transistors (G4-FETs) is presented. Thanks to the multiple inputs of the G4-FET that may be biased independently, the number of transistors in the proposed circuit is dramatically reduced, compared to conventional single-gate MOSFET based multipliers. Only four G4-FETs are needed to build the multiplier core. The circuit is feasible with a standard SOI CMOS process. Two different configurations, both based on the linear modulation of the front-gate threshold voltage by the junction-gates, are presented. This paper addresses the theoretical analysis as well as the preliminary measurement results.

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Role of the bipolar transistor on the hot-carrier-degradation of SOI MOSFETs

Chinese Journal of Aeronautics, 1995

Hot-carrier-induced degradation is a major challenge for shrinking further the size of bulk Si or... more Hot-carrier-induced degradation is a major challenge for shrinking further the size of bulk Si or SOI components. Although there is no evidence that the aging of SOI MOSFETs is more severe than that of bulk Si counterparts, the degradation mechanisms are more complex: (i) not only the front gate but also the buried oxide and related interface may be damaged, (ii) interface coupling allows the front channel to sense the presence of defects at the opposite interface, (iii) the fields are different, and (iv) floating-body effects may come into play. The purpose of this work is to investigate the latter aspect by revealing the main consequences of stresses conducted in floating- and biased-body modes

Depletion-All-Around Operation of the SOI Four-Gate Transistor

IEEE Transactions on Electron Devices, 2007

In the silicon-on-insulator four-gate transistors (G 4 -FETs), the conducting channel can be surr... more In the silicon-on-insulator four-gate transistors (G 4 -FETs), the conducting channel can be surrounded by depletion regions induced by independent vertical metal-oxidesemiconductor gates and lateral JFET gates. This unique conduction mechanism named depletion-all-around (DAA) enables majority carriers to flow in the volume of the silicon film far from the silicon/oxide interfaces. Especially when the interfaces are driven to inversion, the control of the lateral JFET gates on the conduction is maximized, while the sensitivity of the volume channel to the oxide and interface defects is minimized. This leads to excellent analog performance, low noise, and reduced sensitivity to ionizing radiation. The G 4 -FET properties in DAA mode are presented from multiple perspectives: experimental results, 3-D device simulations, and analytical modeling.

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Threshold voltage model of the SOI 4-gate transistor

The operation of the 4-gate transistor (G4-FET) is governed by the charge coupling between front,... more The operation of the 4-gate transistor (G4-FET) is governed by the charge coupling between front, back and lateral gates. A 2D analytical relation for the fully-depleted body potential is derived. The front-interface threshold voltage is expressed as a function of the back and lateral gate voltages for all possible back interface conditions.

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Evidence for reduction of noise and radiation effects in G4FET depletion-all-around operation

The low noise and radiation-hard operation of the SOI Four-Gate transistor (G 4 -FET) is experime... more The low noise and radiation-hard operation of the SOI Four-Gate transistor (G 4 -FET) is experimentally demonstrated. When operated in depletion-all-around (DAA) mode, the G 4 -FET drain current flows in the middle of the silicon film, far from the interfaces. The influence of oxide and interface traps on the conduction channel is suppressed by biasing the front and back gates in depletion or, even better, in inversion. Systematic data show a significant reduction of low-frequency noise as well as a quasi-insensitivity to total-dose radiation effects, up to 10 Mrad. These features come along with superior static characteristics in DAA mode and are attractive for G 4 -FET-based analog circuits.

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