P.C. Bhaskar

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Papers by P.C. Bhaskar

Clustering the documents based on similarity of words and searching the text is major search proc... more Clustering the documents based on similarity of words and searching the text is major search procedure and widely used for large set of documents. Documents can be clustered using many clustering algorithms such as Nearest Neighbor, K-Means, Hierarchical, Graph Theoretic etc [4] [5] [7]. The performance measurement in terms of space complexity and execution time and searched output in terms of accuracy and redundancy of these algorithms is a needful study [3]. This paper mainly focuses on performance measurement of Nearest Neighbor, K-Means and Hierarchical agglomerative clustering algorithms on text documents as well as compares them in terms of space complexity, execution time, accuracy and redundancy. In particular, preprocess the input text document and convert it into the document graph represented in the form of matrix. Then convert that document graph into relation matrix which gives relation (similarity score) among all the nodes from 0 to 1 [2]. Implementation and the resul...

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(Arithmetic and logical) unit, Memory unit

The Conventional digital circuits dissipate (kTln2) joules of heat energy when losing one bit of ... more The Conventional digital circuits dissipate (kTln2) joules of heat energy when losing one bit of information. Thus, if logic gates are designed such that the information bits are not destroyed, the power consumption can be reduced dramatically because the energy dissipation in any conventional system is proportional to the number of bits lost during processing of bit. The reversible circuits do not lose any bits of information because there is one-to-one mapping between inputs and outputs. In the reversible logic we can, not only get the output from input but we can also retrieve input from output. Thus we designed an Efficient Computational system of reversible circuits for an acquisition of analogy data converting into digital data, computing the data and storing a data on FPGA. The system is based on reversible logic hence it dissipate less power than the conventional logical system. The system consist of ADC unit hence the real time data can be converted to digital data and furt...

Monitoring Ecg of Remotely Located Patient Using Matlab

Abstract: Cardiovascular disease is one of the diseases that accounts for high mortality rate acr... more Abstract: Cardiovascular disease is one of the diseases that accounts for high mortality rate across the globe. In today's stressed and busy life people don't have time to visit doctors again and again. Sometimes it happens that people even need immediate on spot treatment which cannot be accomplished with wired technology. This motivates for WSN based system that can monitor remotely located patient. In this paper ECG is extracted using 3 lead ECG clamp and is wirelessly transmitted to doctor workstation in real time using GSM/GPRS SIM300 module. Since, we are dealing with an important parameter that is ECG data integrity is must and is fulfilled using TCP protocol. The main processing element used is ARM7 and ECG signal is efficiently received on PC in MATLAB at doctor's workstation

Smart Agricultural Robot for Spraying Pesticide with Image Processing based Disease Classification Technique

2021 International Conference on Emerging Smart Computing and Informatics (ESCI), 2021

The excellent development of crops decides the different parameters like worth, store consumption... more The excellent development of crops decides the different parameters like worth, store consumption moreover final money-making profits of farming output. On the other hand, there are important factors that are required for the development of agriculture harvesting, which consist of macronutrients, less important nutrients, micronutrients, as well as pesticides. Conventionally, the checking of all the grain, fruit, vegetables, etc development mostly depends on an individual human verdict and is not well-timed or exact. Maintain regular surveillance over crop is an important facet of precision agriculture that uses facts at various crop growth phases. This paper presents an automatic disease classification and pesticide controller based on an Image Processing (IP) technique. Having precise information about the disease for classification and to spray pesticides is very much supportive in enhancing the production efficiency. Compared with manual processes, the proposed automatic disease classification and pesticide controller system can identify the disease in crops and can present a consistent and precise basis for suitable regulation.

Novel E-Voting System with Biometric Authentication and Distributed Server System

International Journal of Innovative Research in Computer and Communication Engineering, 2017

India is the largest democratic country where voting and elections are fundamental to any consens... more India is the largest democratic country where voting and elections are fundamental to any consensus-based society. In India we use the most popular voting system called as an electronic voting system (EVM) for its easy access and less time consuming features, but yet this voting system is not at all efficient and secured one. So we present a Novel Electronic Voting System which is based on biometric authentication and distributed servers approach which provide high security for voting process. Whole voting system is divided into two parts one is a voting machine and another is server system. Raspberry pi 3 model B is a heart of the voting machine. This host minicomputer has the ability to control complete activity of voting process. Voting machine is developed based on biometric authentication and distributed server system. So for authentication purpose we use a biometric database of Aadhar card which is already given from all Indian citizens by the Unique Identification Authority o...

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Particle Swarm Optimization algorithm based Adaptive filter for Removal of Baseline Wander Noise from ECG signal

Electrocardiogram (ECG) is very much susceptible to the Noise and Interference, these are may be ... more Electrocardiogram (ECG) is very much susceptible to the Noise and Interference, these are may be other different noise sources. Due to the different types of Noises and Interferences ECG Signal gets corrupted and hence data will be lost. Different types of Noises and Interferences like Power Line Noise (50 Hz), Base Line Wonder Noise (0.05 Hz), Muscle contraction or External High Frequency Noise etc. This Paper focus on the Base line Wonder Noise Which is having very small frequency component of 0.05 Hz to 5 Hz. This small frequency components overlap with that of the ECG Signal, due to the overlap ECG signal information gets corrupted. Hence removing the Base Line Wonder Noise we use newly developed Swarm optimization algorithm based on Adaptive Filter. Swarm Optimization Algorithm minimize the noise signal which is present in the noisy ECG signal.

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Pre-processing Techniques in Sentiment Analysis through FRN: A Review

The objective of the paper is to demonstrate the viability of analyzing online data. It displays ... more The objective of the paper is to demonstrate the viability of analyzing online data. It displays a framework which after effects pattern investigation that will be shown as results with various segments introducing positive, negative and neutral. It is challenging task to summarize opinion about the products due to diversity and size. Mining online opinion mining is a difficult text classification task of sentiment analysis. Multivariate content technique called Feature Relation Network that considers semantic data, influencing the syntactic connections between n-gram features. FRN empowers the consideration of heterogeneous n-gram features for improved opinion classification, by joining syntactic data about n-gram relations. FRN selects the features in a more computationally effective way than numerous multivariate and hybrid methods. Appropriate feature selection and representation with sentiment analysis, accuracies using support vector mechanism sentiment analysis; the task of t...

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FPGAに基づくクロックゲーティング実施と電力解析のためのプロセッサエンジンの開発【Powered by NICT】

FPGA Implementation of Run-Time Reconfigurable Platform for Bio-Medical Application

2018 Fourth International Conference on Computing Communication Control and Automation (ICCUBEA), 2018

In this article, the use of Field Programmable Gate Array to examine reconfiguration which will h... more In this article, the use of Field Programmable Gate Array to examine reconfiguration which will help into the field of Bio-medical Applications has been focused. The FPGA is reconfigured at real-time to analyse parameters like body temperature, pulse rate, ECG. To implement the application partial reconfiguration is used. In this method, there are two ways 1) Static 2) Dynamic. Configuration of the FPGA before reconfiguration known as static part. When reconfiguration of FPGA is again take place that part is known as the partial reconfigurable part of the system. In first part two sensors are taken as temperature and pulse sensor. In next part ECG sensor is added. The outcomes involve displaying respective values in particular conditions using DPR. The above work can be successfully carried out for patient to monitor their health condition and the data is seen on IoT at remote location.

Design and Implementation of FPGA Based 32 Bit Floating Point Processor for DSP Application

2018 Fourth International Conference on Computing Communication Control and Automation (ICCUBEA), 2018

The floating point arithmetic operations have discovered applications in the various different fi... more The floating point arithmetic operations have discovered applications in the various different fields for the necessities for requirments high precision operation because of its incredible dynamic range, high accuracy and fast arithmetic operations. High accuracy is needed for the design and research of the floating point processing units. With the expanding necessities for the floating point operations for the fast high speed data signal processing and the logical operation, the requirements for the high-speed hardware floating point arithmetic units have turned out to be increasingly requesting. This paper deals with the design and implementation of the 32-bit floating point Processor with MAC unit for signal processing application. The Linear convolution and Circular convolution of signals is verified. The necessary code is written in the language Verilog. Xilinx 14.7 suite is used for software development and then implementation on Spartan 6 board. The designed DSP has instructions set and consists of 32-bit ALU, 32-bit X 32-bit parallel multiplier for single-cycle MAC operation, 2 addressing modes, 31 auxiliary register arithmetic units.

Processor Design Using 32 Bit Single Precision Floating Point Unit

International Journal of Trend in Scientific Research and Development, 2018

The floating point operations have discovered concentrated applications in the various different ... more The floating point operations have discovered concentrated applications in the various different fields for the necessities for high precision operation because of its incredible dynamic range, high exactness and simple operation rules. High accuracy is needed for the design and research of the floating point processing units. With the expanding necessities for the floating point operations for the fast high speed data signal processing and the logical operation, the requirements for the high-speed hardware point arithmetic units have turned out to be increasingly requesting. The ALU is a standout amongst the most essential segments in a processor, and is ordinarily the piece of the processor that is outlined first. In this paper, a fast IEEE754 32-bit floating point arithmetic unit designed using VHDL code has been presented and all operations of addition got tested on Xilinx and verified successfully.

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Run-Time Re-configuration using FPGA for Bio-Medical Application

International Journal of Trend in Scientific Research and Development, 2018

Now-a-days, FPGAs are even used as prototyping devices. With the ongoing technologies to build th... more Now-a-days, FPGAs are even used as prototyping devices. With the ongoing technologies to build these devices, FPGAs are becoming larger, faster and more accurate. With the proper development environments, FPGAs can also be used in end products to provide specialized features that are not always possible with ASIC chips such as in-field updates of hardware. Partial Re-configuration can be used to maximize the resource utilization in FPGAs. The partial re configuration with FPGA can be used in Bio application at run-time. This application can be considered to monitor and measure various health parameters viz., Body-Temperature, Heart Rate, ECG, Oxygen Saturation and Blood-Pressure etc. In this research article, the runtime partial reconfiguration using VHDL coding in Xilinx tool has been performed.

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Real time ECG Monitoring: A Review

International Journal of Trend in Scientific Research and Development, 2017

Day by day the scope & use of the electronics concepts in bio-medical field is increasing step by... more Day by day the scope & use of the electronics concepts in bio-medical field is increasing step by step. In this paper the review of newly developed concepts is done for the monitoring of the ECG signal. This paper also reviews a power and area efficient electrocardiogram (ECG) acquisition and signal processing application sensor node. Further the study of IoT frame work for ECG monitoring has been carried out.

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Optimized Reconfigurable ASIP of FIR Filter using FPGA

Reconfigure ability denotes reconfigurable computing capabilities of a system, so that its behavi... more Reconfigure ability denotes reconfigurable computing capabilities of a system, so that its behavior can be changed by reconfiguration with improvements in capacity & performance. Application specific instruction set processor is bridge between ASIC & DSP. This research works based on Xilinx System Generator which support for runtime reconfiguration which further controls ASIP.FIR (Finite Impulse Response) filter is configured for different taps & methods.1-D signal i.e., ECG (Electrocardiogram) is taken for filtration, which having Gaussian noise also known as EMG noise. A generalized instrumentation signal which needs Filters are also taken for computation. This proposed work is implemented on Spartan xc3s500e-4fg320 board and pin N17, H18 are configured as reconfigurable switch which will give facility for applying different type of filter at run time. The results of different filter design techniques are analyzed using Matlab simulation tool and performance is evaluated based on ...

Transmission of Arm Based Real Time Ecg for Monitoring Remotely Located Patient

International Journal of Research in Engineering and Technology, 2014

The development of patient monitoring system is of great importance in today's stressed and busy ... more The development of patient monitoring system is of great importance in today's stressed and busy world where people even don't have time to visit doctors again and again. The need of instant medical help is also increasing day by day and can be achieved with wireless technology thereby motivating for wireless patient monitoring system. Also among all the diseases Cardiovascular is one that accounts for high mortality rate across the globe. So, the proposed system uses the key concept of wireless sensor network and focuses on ECG signal. This system relies on 3 lead ECG clamp to capture real time ECG of the patient and GSM/GPRS SIM300 module for real time wireless transmission.. Since, we are dealing with an important parameter that is ECG data integrity is must and is accomplished using TCP protocol. The main processing element used is ARM7 and ECG signal is efficiently received on PC in MATLAB at doctor workstation.

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Mining Web Data Based on Ontology and SWRL

International Journal of Information and Education Technology, 2012

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Reduction of Power Line Interference in Ecg Signal Using Fir Filter

Filtering of power line interference is very meaningful in the measurement of biomedical events r... more Filtering of power line interference is very meaningful in the measurement of biomedical events recording, particularly in the case of recording signals as weak as the ECG. The available filters for power line interference either need a reference channel or regard the frequency as fixed 50/60Hz. Methods of noise reduction have decisive influence on performance of all electro-cardiographic (ECG) signal processing systems. This work deals with problems of power line interference reduction. Some analogue and digital approaches to this problem are presented and its properties, advantages and disadvantages are shown. Present paper deals with design and development of digital FIR equiripple filter. The basic ECG has the frequency range from .5Hz to 100Hz.

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Design of Viterbi Decoder for Noisy Channel on FPGA

ijser.org

The problem of survival memory management of a Viterbi Decoder (VD) was solved by introducing a p... more The problem of survival memory management of a Viterbi Decoder (VD) was solved by introducing a pointer implementation for the register exchange (RE) method, where a pointer is assigned to each row of memory in the SMU. The content of the pointer which points to one row of memory is altered to point to another row of memory, instead of copying the contents of the first row to the second. In this paper, the onepointer VD is proposed; if the initial state of the convolutional encoder is known, the entire survivor memory unit (SMU) is reduced to only one row. Because the decoded data are generated in the required order, even this row of memory is dispensable. Thus, the one-pointer architecture, referred to as memory less Viterbi Decoder (MLVD), reduces the power consumption of a traditional trace back (TB) VD by approximately 50 percent. A prototype of the MLVD with a one third convolutional code rate and a constraint length of nine is mapped into a Xilinx.

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Reduction of Power Line Interference in Ecg

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Speech Compression using DWT in FPGA

ijser.org

The paper gives the details about the speech compression using discrete wavelet transform in FPGA... more The paper gives the details about the speech compression using discrete wavelet transform in FPGA. In today's world multimedia files are used, storage space required for these files is more and sound files have no option so ultimate solution for this is compression. Compression is nothing but high input stream of data converted into smaller size. Compression is done for all, such as image, data; signals. Here speech compression technique is used and done using DWT. For this purpose only single level implementation is done to get compressed signal, and this is implemented in FPGA by using VHDL code. In this technique DWT code is written in VHDL that include separation of high level component and low level component from given input wav file and after separating these components down sampling is done and we get the compressed speech signal by keeping only approximation part of the result. The compressed speech signal was read back after up-sampling was performed. The resulting compressed signal is with some noise and future work is to reduce noise.

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P.C. Bhaskar

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