FPGA-based combined architecture for stream categorization and intrusion detection
Abstract This paper presents a working solution for the MEMOCODE 2010 design contest. The design ... more Abstract This paper presents a working solution for the MEMOCODE 2010 design contest. The design presented in this paper is implemented in the Xilinx V5LX330 FPGA as a custom circuit. The solution implements pattern matching logic for all the mandatory and optional ...
The XPP Architecture and Its Co-simulation Within the Simulink Environment
This paper offers an overview of the XPP, a coarse-grained reconfigurable architecture, and prese... more This paper offers an overview of the XPP, a coarse-grained reconfigurable architecture, and presents a solution for its integration into a Simulink design flow for rapid prototyping. This includes a system-level co-simulation followed by the automated code generation for an embedded target platform. In order to realize this functionality, a custom Simulink module has been developed. During the co-simulation phase, it acts as a wrapper for an external simulator, whereas when code is generated, it is responsible for generating the appropriate function calls for communicating with the XPP device. Of these two aspects, only the co-simulation is considered here.
An Industrial/Academic Configurable System-on-Chip Project (CSoC): Coarse-Grain XXP-/Leon-Based Architecture Integration
Abstract Summary form only given. This paper describes the actual status and results of a dynamic... more Abstract Summary form only given. This paper describes the actual status and results of a dynamically Configurable System-on-Chip (CSoC) integration, consisting of a SPARC-compatible Leon processor-core, a commercial coarse-grain XPP-array of suitable size ...
The eXtreme Processing Platform (XPPTM) is a new runtime-reconfigurable data processing architect... more The eXtreme Processing Platform (XPPTM) is a new runtime-reconfigurable data processing architecture. It is based on a hierarchical array of coarsegrain, adaptive computing elements, and a packet-oriented communication network. The strength of the XPPTM technology originates from the combination of array processing with unique, powerful run-time reconfiguration mechanisms. Parts of the array can be configured rapidly in parallel while neighboring computing elements are processing data. Reconfiguration is triggered externally or even by special event signals originating within the array, enabling self-reconfiguring designs. The XPPTM architecture is designed to support different types of parallelism: pipelining, instruction level, data flow, and task level parallelism. Therefore this technology is well suited for applications in multimedia, telecommunications, simulation, signal processing (DSP), graphics, and similar stream-based application domains. The anticipated peak performance of the first commercial device running at 150MHz is estimated to be 57.6 GigaOps/sec, with a peak I/O bandwidth of several GByte/sec. Simulated applications achieve up to 43.5 GigaOps/sec (32-bit fixed point).
Dynamic Reconfiguration for Irregular Code Using FNC-PAE Processor Cores
This paper describes PACT XPP Technologies' Func- tion-PAE (FNC-PAE) Processor Core which wa... more This paper describes PACT XPP Technologies' Func- tion-PAE (FNC-PAE) Processor Core which was designed for executing irregular, control-flow dominated code efficiently in embedded systems. It combines aspects of dynamically reconfi- gurable coarse-grain arrays and VLIW processors. The silicon- proven FNC-PAE Cores are tightly integrated with the XPP reconfigurable dataflow array. We present the FNC-PAE archi- tecture, its development environment (assembler, C compiler, and simulator), application examples, and performance data collected from the fully working prototype chip.
Using function folding to improve silicon efficiency of reconfigurable arithmetic arrays
This work presents function folding, a design principle to improve the silicon efficiency of reco... more This work presents function folding, a design principle to improve the silicon efficiency of reconfigurable arithmetic (coarse-grain) arrays. Though highly parallel implementations of DSP algorithms have been demonstrated on these arrays, the overall silicon efficiency of current devices is limited by both the large numbers of ALUs required in the array and by the only moderate speeds which are achieved. The operating frequencies are mainly limited by the requirements of nonlocal routing connections. We present a novel approach to overcome these limitations: In function folding, a small number of distinct operators belonging to the same configuration are folded onto the same ALU, i.e. executed sequentially on one processing element. The ALU is controlled by a program repetitively executing the same instruction sequence. Data only required locally is stored in a local register file. This sequential approach uses the individual ALU resources more efficiently, while all processing elements of the array work in parallel as in current devices. Additionally, the ALUs and local registers can be clocked with a higher frequency than the (nonlocal) routing connections. Overall, a higher computational density than in current devices results.
Reconfigurable Processor Architectures for Mobile Phones
This paper describes a new dynamically configurable system-on-chip (CSoC) concept and integration... more This paper describes a new dynamically configurable system-on-chip (CSoC) concept and integration, consisting of an ARM7 EJS processor-core, a coarse-grain 4×4 XPP-array from PACT XPP Technologies AG, and application-tailored global/local memory topology with efficient Amba-based communication interfaces. The system and introduced CSoC architecture is optimized for the mobile communication algorithm scenario. The paper gives an overview of the overall system concept, the hardware datapath structures and their integration as well as discussing some selected application implementation results within this target area.
Architecture, Memory and Interface Technology Integration of an Industrial/Academic Configurable System-on-Chip (CSoC
This paper describes the actual status and results of a dy-namically Configurable System-on-Chip ... more This paper describes the actual status and results of a dy-namically Configurable System-on-Chip (CSoC) integra-tion, consisting of a SPARC-compatible LEON processor-core, a commercial coarse-grain XPP-array of suitable size from PACT XPP Technologies ...
Stream-based XPP Architectures in Adaptive System-on-Chip Integration
This chapter describes the structures and principles of stream-based, reconfigurable XPP Architec... more This chapter describes the structures and principles of stream-based, reconfigurable XPP Architectures from PACTXPP Technologies AG (Munich, Germany). The status of an adaptive System-on-Chip (SoC) integration is given, consisting of a SPARC-compatible LEON processor-core, a coarse-grain XPP-array of suitable size, and efficient multi-layer Amba-based communication interfaces. In addition PACTs newest XPP architectures are described, realizing a new runtime reconfigurable data processing technology that replaces the concept of instruction sequencing by configuration sequencing with high performance application areas envisioned from embedded signal processing to co-processing in different DSP-like and mobile application environments. The underlying programming model is motivated by the fact, that future oriented applications need to process streams of data decomposed into smaller sequences which are processed in parallel. Finally, first-time-right commercial chip synthesis were performed successfully onto 0.13 µm STMicro CMOS technology.
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Papers by Martin Vorbach