Malcolm Shute

Cobweb-2: Structured specification of a wafer-scale supercomputer

Springer eBooks, 1987

* Computer Science Department, The City University, Northampton Square, London EC1 VOHB, UK. ** D... more

Multiprocessor Computer Architectures

1. Categorising Parallel Computer Architectures (M.J. Shute). 2. The Experimental ALICE Machine (... more 1. Categorising Parallel Computer Architectures (M.J. Shute). 2. The Experimental ALICE Machine (M.J. Reeve and S. Wright). 3. The FLAGSHIP Parallel Machine (P. Watson). 4. Experiments with the ZAPP Virtual Tree Architecture (D.L. McBurney and M.R. Sleep). 5. GRIP - A High-Performance Architecture for Parallel Graph Reduction (S.L. Peyton Jones, C. Clack, J. Salkild and M. Hardie). 6. COBWEB-2 A Declarative Language Multiprocessor (P. Anderson, D. Bolton, C. Hankin, P. Kelly and P. Osmon). 7. The MANCHESTER DATAFLOW Project (C. Kirkham). 8. The AMT DAP 500 System (A.G. Bale, J. Litt and C.J. Pavelin). 9. A Bit-Serial Systolic Back-Projection Engine (R. Bayford). 10. The CLIP7 Programme (T.J. Fountain). 11. Reconfigurable Transputer Processor Architectures (D.A. Nicole). 12. Conclusions (T.J. Fountain). Index.

Functional programming aspects of wafer scale integration

Microelectronics Journal, 1988

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Abotec

ACM SIGPLAN Notices, 1993

The trial-and-error method, iteratively appfied, is invariably involved in any kind of design wor... more The trial-and-error method, iteratively appfied, is invariably involved in any kind of design work, with much backof-the-envelope calculation to guide the process. In this, the 'what-if' game is a very useful tactic in the search for unexpected solutions in complex design spaces, made all the more effective by the availability of automated interpreters. These are needed to perform the tedious re-calculation of the model each time a change is made to a small part, so that the designer can react to promising or discouraging results, and proceed quickly to the next iteration of the design. In the financial world, the interpreter generally takes the form of the spread-sheet, of which Quattro is a fine example (Parks 1992); in mathematics it takes the form of packages such as Mathematica (Wolfram 1988). Neither of these is ideally tailored for engineering design, and so Abotec was developed when the author had a need of such a tool. There are four main characteristics which fit Abotec for its purpose: (a) it works with floating-point numbers throughout; (b) it uses a richer than normal set of arithmetic operators and functions; (c) it uses mnemonic labelling throughout; and, most importantly (d) it treats all variables as having an upper and lower bound. It is this, its ability to evaluate not just the expected answer but its expected tolerance, as described in Section 2 below, which sets Abotec apart from any other interpretive tool for engineering design. Sections 3 and 4 comment on the use of Abotec as a practical design tool; but first, Section 1 briefly outlines the syntax of the calculator.

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Parallel computer architecture

Fifth generation wafer architecture

Cobweb-2: Structured specification of a wafer-scale supercomputer

Lecture Notes in Computer Science, 1987

* Computer Science Department, The City University, Northampton Square, London EC1 VOHB, UK. ** D... more

Cobweb — A combinator reduction architecture

Lecture Notes in Computer Science, 1985

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Detect a monopole

New Scientist, 2009

You report that bird species are hopping on and off the critically endangered species list due to... more

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Planet X – 1

New Scientist, 2009

Set-aside for fuel

New Scientist, 2006

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Perfect relative pitch

New Scientist, 2011

In the dark?

New Scientist, 2012

Lucky me

New Scientist, 2012

New Scientist, 2012

New Scientist, 2010

The implementation of functional programming languages

Microprocessors and Microsystems, 1987

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An implementation of a 16 bit processor using only 600 transistors

Microelectronics Journal, 1984

This paper describes an implementation of a simple processor which was described in Microe/ectron... more This paper describes an implementation of a simple processor which was described in Microe/ectronicsJourna/, vol. 15, No. 3. That paper considered only how a programmer might visualise the machine. This paper describes the implementation of the machine at the register-transfer level, using a description written in the simulation language ISP'. The operation of the machine is then described, and a few conclusions about its performance are made.

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A design for a 16 bit processor using only 600 transistors

Microelectronics Journal, 1984

1he trend in modem hardware design (especially in that of processors) has been away from unsophis... more 1he trend in modem hardware design (especially in that of processors) has been away from unsophisticated designs, and towards the implementation of highly functional systems. However, there are still some applications for which unrefined systems have a place. In these, ease of using the device is sacrificed for small physical size. Often there is a need to be able to insert an "extra" processor into a small space (for instance on a memory chip); the need for high yields from a wafer of semiconductor is another possible reason for requiring such a small processor, this time as a stand-alone device. This report describes the design of a simple sixteen bit processor which uses only 600 transistors in its implementation. Understandably, the power of the processor, the "NVDAC', is very limited. However, this report sets out to demonstrate that many of the savings have been made by optimising the usa of the hardware which is provided, and that the resultant design has more power than its small size would suggest.

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Pascal for FORTRAN programmers

Computer Languages, 1985

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