Papers by Tomasz Madajczak
Springer eBooks, 2006
This document presents a new method for implementing critical sections in the shared memory paral... more This document presents a new method for implementing critical sections in the shared memory parallel architectures such as multithreaded multiprocessors integrated on a die. The method bases on Shared Explicit Cache System (SHECS) implemented in the multiprocessor. The document presents the concept of system architecture equipped with SHECS, the algorithm to implement operating system or application level locking service, and the results obtained with the method simulation on the network processor Intel 1 IXP2800.
Integrating SHECS-Based Critical Sections with Hardware SMP Scheduler in TLP-CMPs
This document presents the concept of integrating the SHECS (shared explicit cache system)-based ... more This document presents the concept of integrating the SHECS (shared explicit cache system)-based critical sections with SMP scheduler to obtain the efficient general purpose hardware mutual exclusion facility in the TLP-CMP (thread-level parallelism-chip multiprocessing) SMP (symmetric multiprocessing) architectures. There are presented two solutions - the first integrates the SHECS-based CS with software multi-queue SMP scheduler, the second integrates the SHECS-based
Parallel Computing in Electrical Engineering, Sep 7, 2004
Modern network processors deliver a set of methods for implementing critical sections. A number o... more Modern network processors deliver a set of methods for implementing critical sections. A number of them rely on specific hardware support and capabilities, while software techniques are still available when hardware support is not flexible enough. Network processors are dedicated to packet processing and their main goal is to achieve the best possible packet processing performance. Therefore, when choosing the implementation method for a particular problem that will be protected by a critical section, the aim must me for the method to influence the overall system performance A wrongly implemented critical section can very easily degrade the level of parallelism and in consequence the performance of the whole system. Sometimes even correctly implemented critical sections can negatively impact the speed of paths that do not need to be protected with a critical section.
Parallel Computing in Electrical Engineering, Sep 7, 2004
This document presents a theoretical analysis of stateof-the-art hardware threading approaches su... more This document presents a theoretical analysis of stateof-the-art hardware threading approaches such as Switch on Event Multi Threading (SoEMT) and Simultaneous Multi Threading (SMT). It proposes that the On-Demand Virtual Single-Instruction-Multiple-Data (ODVSIMD) abstraction model is a very efficient method of hardware threading in certain scenarios. The principles of ODVSIMD abstraction model are defined. Then, there is a proposition of the application for this abstraction model that is the data-driven automated loop partitioning. The document shows how the DOALL and DOACROSS loops can be parallelized with auto-partitioning to the ODVSIMD abstraction. This document then presents the results of parallel execution of both loop types. The results are obtained with a worksheet simulation. The document also discusses the main differences between SoEMT and SMT architectures in the context achievable performance.
Scheduling packet processing
System to process packets according to an assigned sequence number
Performing Function Calls Using Single Instruction Multiple Data (SIMD) Registers
Network processor with content addressable memory (CAM) mask
Lecture Notes in Computer Science, 2006
This document presents a new method for implementing critical sections in the shared memory paral... more This document presents a new method for implementing critical sections in the shared memory parallel architectures such as multithreaded multiprocessors integrated on a die. The method bases on Shared Explicit Cache System (SHECS) implemented in the multiprocessor. The document presents the concept of system architecture equipped with SHECS, the algorithm to implement operating system or application level locking service, and the results obtained with the method simulation on the network processor Intel 1 IXP2800.
Parallel Computing in Electrical Engineering, International Conference on
This document presents a theoretical analysis of stateof-the-art hardware threading approaches su... more This document presents a theoretical analysis of stateof-the-art hardware threading approaches such as Switch on Event Multi Threading (SoEMT) and Simultaneous Multi Threading (SMT). It proposes that the On-Demand Virtual Single-Instruction-Multiple-Data (ODVSIMD) abstraction model is a very efficient method of hardware threading in certain scenarios. The principles of ODVSIMD abstraction model are defined. Then, there is a proposition of the application for this abstraction model that is the data-driven automated loop partitioning. The document shows how the DOALL and DOACROSS loops can be parallelized with auto-partitioning to the ODVSIMD abstraction. This document then presents the results of parallel execution of both loop types. The results are obtained with a worksheet simulation. The document also discusses the main differences between SoEMT and SMT architectures in the context achievable performance.
Parallel Computing in Electrical Engineering, International Conference on
Modern network processors deliver a set of methods for implementing critical sections. A number o... more Modern network processors deliver a set of methods for implementing critical sections. A number of them rely on specific hardware support and capabilities, while software techniques are still available when hardware support is not flexible enough. Network processors are dedicated to packet processing and their main goal is to achieve the best possible packet processing performance. Therefore, when choosing the implementation method for a particular problem that will be protected by a critical section, the aim must me for the method to influence the overall system performance A wrongly implemented critical section can very easily degrade the level of parallelism and in consequence the performance of the whole system. Sometimes even correctly implemented critical sections can negatively impact the speed of paths that do not need to be protected with a critical section.
Integrating SHECS-Based Critical Sections with Hardware SMP Scheduler in TLP-CMPs
International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06)
This document presents the concept of integrating the SHECS (shared explicit cache system)-based ... more This document presents the concept of integrating the SHECS (shared explicit cache system)-based critical sections with SMP scheduler to obtain the efficient general purpose hardware mutual exclusion facility in the TLP-CMP (thread-level parallelism-chip multiprocessing) SMP (symmetric multiprocessing) architectures. There are presented two solutions - the first integrates the SHECS-based CS with software multi-queue SMP scheduler, the second integrates the SHECS-based
Uploads
Papers by Tomasz Madajczak