An asynchronous 2-D discrete cosine transform chip
Proceedings Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems
This paper describes a fully asynchronous two-dimensional discrete cosine transform chip. The chi... more This paper describes a fully asynchronous two-dimensional discrete cosine transform chip. The chip has a fixed block size of 8×8 pixels and uses bit-serial arithmetic. The chip was fabricated through MOSIS using a 0.8 μ double-metal CMOS process. The 49.5 mm2 core uses ~162,000 transistors. The chip operates from 0.65 V to 7.0 V, but its pixel rate at 5.0
NULL Convention Logic/sup TM/: a complete and consistent logic for asynchronous digital circuit synthesis
Proceedings of International Conference on Application Specific Systems, Architectures and Processors: ASAP '96
... Abstract NULL Convention Logic (NCL) is a symbolically complete logic which expresses process... more ... Abstract NULL Convention Logic (NCL) is a symbolically complete logic which expresses process completely in terms of the logic itself and inherently and conveniently expresses asynchronous digital circuits. The traditional ...
Abstract : A functional/graphical approach is used to assess the fault tolerance of the Digital A... more Abstract : A functional/graphical approach is used to assess the fault tolerance of the Digital Avionics Information System (DAIS), a real-time federated multicomputer digital avionics system. Two separate assessments are made; first the functional/graphical approach is used to assess the fault tolerance of the DAIS architecture, then the utility of the functional/graphical approach itself is considered. The functional/graphical approach used has two complementary aspects; a functional characterization of fault phenomena, and a graphical approach to the representation of system behavior, both for normal operations and in response to faults. The graphical representation used is based on the LOGOS system description schema, which uses two associated graphs, a control graph and a data graph, to represent a process or activity. The study extends earlier functional/graphical studies of individual, isolated fault tolerance mechanisms, to the assessment of a complex large scale digital system. The assessment begins by modeling top level DAIS control functions and includes DAIS master executive functions and top level functions from a potential DAIS application.
Design of asynchronous RISC CPU register-file Write-Back queue
2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2015
This paper presents the comparison results of Area, Performance and Power of FIFO and Data-Queue ... more This paper presents the comparison results of Area, Performance and Power of FIFO and Data-Queue on a logically determined Null Convention Logic RISC CPU register file Write-Back circuit. A shift register block implemented using Delay-Insensitive techniques operates in a way that is identical to a FIFO. In this paper, we illustrate the architectures of the Delay-Insensitive Asynchronous Data-Queue and FIFO and analyze the characteristics of these circuits. This comparison results can be also used to the other buffering unit of the CPU such as scoreboard for Dynamic scheduling or Cache Controller memory interface circuits.
... to the development of the technology. Jerry Sobelman formu-lated the gate implementations and... more ... to the development of the technology. Jerry Sobelman formu-lated the gate implementations and with the assistance of Jason Hinze designed the early experimental test chips. Jordi Cortadella of the Universitat Polite`cnica ...
A method and apparatus relating to the real time automatic detection and classification of charac... more A method and apparatus relating to the real time automatic detection and classification of characteristic type surface imperfections occurring on the surfaces of material of interest such as moving hot metal slabs produced by a continuous steel caster. A data camera transversely scans continuous lines of such a surface to sense light intensities of scanned pixels and generates corresponding voltage
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Papers by Karl Fant