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Joshua Yi

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Papers by Joshua Yi

As Chip Architects and Manufacturers Plumb Ever-Smaller Process Technologies, New Species of Faults Are Compromising Device Reliability

Informed Prefetching for Indirect Memory Accesses

ACM Transactions on Architecture and Code Optimization, 2020

Indirect memory accesses have irregular access patterns that limit the performance of conventiona... more Indirect memory accesses have irregular access patterns that limit the performance of conventional software and hardware-based prefetchers. To address this problem, we propose the Array Tracking Prefetcher (ATP), which tracks array-based indirect memory accesses using a novel combination of software and hardware. ATP is first configured by special metadata instructions, which are inserted by programmer or compiler to pass data structure traversal knowledge. It then calculates and issues prefetches based on this information. ATP also employs a novel mechanism for dynamically adjusting prefetching distance to reduce early or late prefetches. ATP yields average speedup of 2.17 as compared to a single-core without prefetching. By contrast, the speedup for conventional software and hardware-based prefetching is 1.84 and 1.32, respectively. For four cores, the average speedup for ATP is 1.85, while the corresponding speedups for software and hardware-based prefetching are 1.60 and 1.25, r...

Impact of Future Technologies on Architecture

IEEE Micro, 2016

Proprietary versus Open Instruction Sets

IEEE Micro, 2016

Effects of Processor Parameter Selection on Simulat ion Results

Due to cost, time, and flexibility constraints, simulators are nee ded to explore the design spac... more Due to cost, time, and flexibility constraints, simulators are nee ded to explore the design space when developing a new processor architecture as well as w hen evaluating the performance of new compiler-based and microarchitectural mechanisms. However, improperly choosing the processor parameters, such as the cache size, the associativi ty, the number of functional units, and so forth, can significantly

Evaluating the efficacy of statistical simulation for design space exploration

2006 IEEE International Symposium on Performance Analysis of Systems and Software

Recent research has proposed statistical simulation as a technique for fast performance evaluatio... more Recent research has proposed statistical simulation as a technique for fast performance evaluation of superscalar microprocessors. The idea in statistical simulation is to measure a program's key performance characteristics, generate a synthetic trace with these characteristics, and simulate the synthetic trace. Due to the probabilistic nature of statistical simulation the performance estimate quickly converges to a solution, making it an attractive technique to efficiently cull a large microprocessor design space. In this paper, we evaluate the efficacy of statistical simulation in exploring the design space. Specifically, we characterize the following aspects of statistical simulation: (i) fidelity of performance bottlenecks, with respect to cycleaccurate simulation of the program, (ii) ability to track design changes, and (iii) trade-off between accuracy and complexity in statistical simulation models. In our characterization experiments, we use the Plackett & Burman (P&B) design to systematically stress statistical simulation by creating different performance bottlenecks. The key results from this paper are: (1) Synthetic traces stress at least the same 10 most significant processor performance bottlenecks as the original workload, (2) Statistical simulation can effectively track design changes to identify feasible design points in a large design space of aggressive microarchitectures, (3) Our evaluation of 4 statistical simulation models shows that although a very detailed model is needed to achieve a good absolute accuracy in performance estimation, a simple model is sufficient to achieve good relative accuracy, and (4) The P&B design technique can be used to quickly identify areas to focus on to improve the accuracy of the statistical simulation model.

Statistical Techniques for Computer Performance Analysis

Performance Evaluation and Benchmarking, 2005

Instruction Precomputation

Chapman & Hall/CRC Computer & Information Science Series, 2005

Adaptive simulation sampling using an Autoregressive framework

2009 International Symposium on Systems, Architectures, Modeling, and Simulation, 2009

Software simulators remain several orders of magnitude slower than the modern microprocessor arch... more Software simulators remain several orders of magnitude slower than the modern microprocessor architectures they simulate. Although various reduced-time simulation tools are available to accurately help pick truncated benchmark simulation, they either come with a need for offline analysis of the benchmarks initially or require many iterative runs of the benchmark. In this paper, we present a novel sampling simulation method, which only requires a single run of the benchmark to achieve a desired confidence interval, with no offline analysis and gives comparable results in accuracy and sample sizes to current simulation methodologies. Our method is a novel configuration independent approach that incorporates an Autoregressive (AR) model using the squared coefficient of variance (SCV) of Cycles per Instruction (CPI). Using the sampled SCVs of past intervals of a benchmark, the model computes the required number of samples for the next interval through a derived relationship between number of samples and the SCVs of the CPI distribution. Our implementation of the AR model achieves an actual average error of only 0.76% on CPI with a 99.7% confidence interval of ±0.3% for all SPEC2K benchmarks while simulating, in detail, an average of 40 million instructions per benchmark.

Evaluating Benchmark Subsetting Approaches

2006 IEEE International Symposium on Workload Characterization, 2006

To reduce the simulation time to a tractable amount or due to compilation (or other related) prob... more To reduce the simulation time to a tractable amount or due to compilation (or other related) problems, computer architects often simulate only a subset of the benchmarks in a benchmark suite. However, if the architect chooses a subset of benchmarks that is not representative, the subsequent simulation results will, at best, be misleading or, at worst, yield incorrect conclusions. To address this problem, computer architects have recently proposed several statistically-based approaches to subset a benchmark suite. While some of these approaches are well-grounded statistically, what has not yet been thoroughly evaluated is the: 1) Absolute accuracy, 2) Relative accuracy across a range of processor and memory subsystem enhancements, and 3) Representativeness and coverage of each approach for a range of subset sizes. Specifically, this paper evaluates statistically-based subsetting approaches based on principal components analysis (PCA) and the Plackett and Burman (P&B) design, in addition to prevailing approaches such as integer vs. floating-point, core vs. memory-bound, by language, and at random. Our results show that the two statistically-based approaches, PCA and P&B, have the best absolute and relative accuracy for CPI and energy-delay product (EDP), produce subsets that are the most representative, and choose benchmark and input set pairs that are most well-distributed across the benchmark space. To achieve a 5% absolute CPI and EDP error, across a wide range of configurations, PCA and P&B typically need about 17 benchmark and input set pairs, while the other five approaches often choose more than 30 benchmark and input set pairs.

Improving Processor Performance by Simplifying and Bypassing Trivial Computations

During the course of a program's execution, a processor performs many trivial computations; ... more During the course of a program's execution, a processor performs many trivial computations; that is, computations that can be simplified or where the result is zero, one, or equal to one of the input operands. This paper shows that, despite compiling a program with aggressive optimizations (-O3), approximately 30% of all arithmetic instructions, which account for 12% of all dynamic instructions, are trivial computations. The amount of trivial computation is not heavily dependent on the program's specific input values. Our results show that eliminating trivial computations dynamically at run-time yields an average speedup of 8% for a typical processor. Even for a very aggressive processor (i.e. one with no functional unit constraints), the average speedup is still 6%. It also is important to note that the area cost (i.e. hardware) required to dynamically detect and eliminate these trivial computations is very low, consisting of only a few comparators and multiplexers.

An Analysis of the Potential for Global Level Value Reuse in the SPEC 95 and SPEC 2000 Benchmarks

This paper analyzes the amount of redundant computation at a global level within selected benchma... more This paper analyzes the amount of redundant computation at a global level within selected benchmarks of the SPEC 95 and SPEC 2000 benchmark suites. Local level redundant computations are redundant computations that are the result of a single static instruction (i.e. PC dependent) while global level redundant computations are redundant computations that are the result of multiple static instructions (i.e. PC independent). The results show that for all benchmarks, less than 10% of the input sets account more than 65% of the dynamic instructions; an input set is defined as an instruction's opcode, input operands, and PC. In addition, for 8 of the 15 benchmarks profiled in this paper, less than 10% of the input sets accounted for over 90% of the dynamic instructions. Additionally, less than 1000 (0.14%) of the most frequently occurring input sets accounted for 19.4% - 95.5% of the dynamic instructions. Furthermore, more potential for value reuse exists at the global level as compar...

A Statistically Rigorous Approach for Improving Simulation Methodology

Due to cost, time, and flexibility constraints, simulators are often used to explore the design s... more Due to cost, time, and flexibility constraints, simulators are often used to explore the design space when developing new processor architectures, as well as when evaluating the performance of new processor enhancements. However, despite this dependence on simulators, statistically rigorous simulation methodologies are not typically used in computer architecture research. A formal methodology can provide a sound basis for drawing conclusions gathered from simulation results by adding statistical rigor, and consequently, can increase confidence in the simulation results. This paper demonstrates the application of a rigorous statistical technique to the setup and analysis phases of the simulation process. Specifically, we apply a Plackett and Burman design to: 1) identify key processor parameters, 2) classify benchmarks based on how they affect the processor, and 3) analyze the effect of processor performance enhancements. Our technique expands on previous work by applying a statistic...

The impact of wrong-path memory references in cache-coherent multiprocessor systems

Journal of Parallel and Distributed Computing, 2007

The core of current-generation high-performance multiprocessor systems is out-of-order execution ... more The core of current-generation high-performance multiprocessor systems is out-of-order execution processors with aggressive branch prediction. Despite their relatively high branch prediction accuracy, these processors still execute many memory instructions down mispredicted paths. Previous work that focused on uniprocessors showed that these wrong-path (WP) memory references may pollute the caches and increase the amount of cache and memory traffic. On the positive side, however, they may prefetch data into the caches for memory references on the correct-path. While computer architects have thoroughly studied the impact of WP effects in uniprocessor systems, there is no comparable work for multiprocessor systems. In this paper, we explore the effects of WP memory references on the memory system behavior of shared-memory multiprocessor (SMP) systems for both broadcast and directory-based cache coherence. Our results show that these WP memory references can increase the amount of cache-to-cache transfers by 32%, invalidations by 8% and 20% for broadcast and directory-based SMPs, respectively, and the number of writebacks by up to 67% for both systems. In addition to the extra coherence traffic, WP memory references also increase the number of cache line state transitions by 21% and 32% for broadcast and directory-based SMPs, respectively. In order to reduce the performance impact of these WP memory references, we introduce two simple mechanisms-filtering WP blocks that are not likely-to-be-used and WP aware cache replacement-that yield speedups of up to 37%.

Quantifying and Comparing the Impact of Wrong-Path Memory References in Multiple-CMP Systems

Out-of-order execution processors with aggressive branch prediction are the core of current-gener... more Out-of-order execution processors with aggressive branch prediction are the core of current-generation high-performance multiprocessor systems. Despite their relatively high branch prediction accuracies, these processors still execute many memory instructions on the mispredicted path. These wrong-path memory references pollute the caches and increase the amount of memory traffic, but may also prefetch useful data into the caches. For multiprocessor systems, wrong-path memory references also affect the number of writebacks, cache-to-cache transfers, and cache line state transitions. In this paper, we explore the effects that wrong-path memory references have in multiple chip- multiprocessor systems. Our results show that wrong- path memory references increase the amount of L1 and L2 cache traffic by 16% and 35%, respectively, and the traffic on the internal and external networks by 36% and 30%, respectively. These additional L1 and L2 cache replacements increase the number of additio...

Speed versus Accuracy Trade-Offs in Microarchitectural Simulations

IEEE Transactions on Computers, 2007

Due to the long simulation time of the reference input set, computer architects often use reduced... more Due to the long simulation time of the reference input set, computer architects often use reduced time simulation techniques to shorten the simulation time. However, what has not yet been thoroughly evaluated is the accuracy of these techniques relative to the reference input set and with respect to each other. To rectify this deficiency, this paper uses three methods to characterize reduced input set, truncated execution, and sampling-based simulation techniques while also examining their speed versus accuracy trade-off and configuration dependence. Our results show that the three sampling-based techniques, SimPoint, SMARTS, and random sampling, have the best accuracy, the best speed versus accuracy trade-off, and the least configuration dependence. On the other hand, the reduced input set and truncated execution simulation techniques had generally poor accuracy, were not significantly faster than the sampling-based techniques, and were severely configuration dependent. The final contribution of this paper is a decision tree, which can help architects choose the most appropriate technique for their simulations.

Reliability: Is it fortune or fallacy?

IEEE Micro, 2007

Single-threaded vs. multi-threaded

IEEE Micro, 2007

Programming Multicores: Do Applications Programmers Need to Write Explicitly Parallel Programs?

IEEE Micro, 2010

Where Does Security Stand? New Vulnerabilities vs. Trusted Computing

IEEE Micro, 2007