Papers by Dillibabu Shanmugam

Denial of Service Detection System on various platforms
2019 International Carnahan Conference on Security Technology (ICCST)
As the concept of network evolves and diverge for ease of end-to-end communication in a real-time... more As the concept of network evolves and diverge for ease of end-to-end communication in a real-time scenario, the unknown problems also rooted with that as a challenge for users. For instance, an advance method of attacking a network system to make it unusable for the legitimate user is called DDoS attack. DDoS attacks are an annoyance at a minimum, and if they are against a Critical Information Infrastructure(CII) networks or system, they can cause severe damage to network resources, say, service slowdown, communication failure between network users, financial loss and spoil good reputation. In order to protect CII, we developed detection mechanism for DoS and DDoS attacks using machine learning techniques. In this paper, we share our implementation methodology on different platforms (FPGA [1], x86 and PowerPC [2]). In addition, we compare the performance on different platforms using standard dataset(DARPA) and limited number of real time dataset.

Implementation Vulnerability Analysis: A case study on ChaCha of SPHINCS
2020 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)
Deployment of Post Quantum Cryptography(PQC) primitives ensures forward secrecy for today’s commu... more Deployment of Post Quantum Cryptography(PQC) primitives ensures forward secrecy for today’s communication against tomorrow’s quantum adversary. However, these primitives have to be realized in conventional hardware, which may be vulnerable to side-channel attacks. Therefore, vulnerability analysis of these primitives is essential before deployment. In this paper, a NIST favoured digital signature primitive- SPHINCS is taken for analysis. ChaCha and BLAKE are ciphers that form the building blocks of SPHINCS. These ciphers are based on Addition, Rotation, and XOR(ARX) operations. The literature review has shown ARX ciphers to be vulnerable against implementation attacks. In this work, an effective countermeasure for the aforementioned building blocks is explored. This is achieved through the following: Parallel Prefix Adders are taken for addition operation in these ciphers instead of the native adder in Electronic Design Automation(EDA) tools. Distinct profiles are created which include the cipher using a particular adder with its best-suited implementation style. An optimized version of Threshold Implementation(TI) is adopted on the profiles as a countermeasure for the attacks on the unprotected implementations. Finally, we evaluate the protected profiles’ resistance using Test Vector Leakage Assessment(TVLA) and Deep learning techniques. Such an analysis that follows a generic framework will be straightforward to automate. We believe this will serve to be useful for standardization of Threshold Schemes.

IACR Cryptol. ePrint Arch., 2017
Security evaluation of third-party cryptographic IP (Intellectual Property) cores is often ignore... more Security evaluation of third-party cryptographic IP (Intellectual Property) cores is often ignored due to several reasons including, lack of awareness about its adversity, lack of trust validation methodology otherwise view security as a byproduct. Particularly, the validation of low latency cipher IP core on Internet of Things (IoT) devices is crucial as they may otherwise become vulnerable for information theft. In this paper, we share an (Un)intentional way of cipher implementation as IP core(hard) become susceptible against side channel attack and show how the susceptible implementation can be experimentally exploited to reveal secret key in FPGA using power analysis. In this paper our contributions are: First, we present Look-Up Table (LUT) based unrolled implementation of PRINCE [1] block cipher with place and route constraints in FPGA. Second, using power analysis attack we recover 128bit key of PRINCE with complexity of 2. Finally, we conclude the paper with the experimental...

Secure Realization of Lightweight Block Cipher: A Case Study Using GIFT
Security, Privacy, and Applied Cryptography Engineering, 2018
Lightweight block ciphers are predominately useful in resource constrained Internet-of-Things(IoT... more Lightweight block ciphers are predominately useful in resource constrained Internet-of-Things(IoT) applications. The security of ciphers is often overthrown by various types of attacks, especially, side-channel attacks. These attacks make it necessary for us to come up with efficient countermeasure techniques that can revert the effect caused by these attacks. PRESENT inspired block cipher, GIFT is taken for analysis and development of countermeasure. In this paper: Firstly, we have implemented the GIFT algorithm in (Un)rolled fashion for vulnerability analysis. Then cipher key is revealed successfully using correlation power analysis. We proposed various protected implementation profiles using Threshold Implementation (TI) and realization techniques carried out on the GIFT algorithm. We believe, the case study widens the choice of level-of-security with trade-off factors for secure realization of the cipher based on application requirement.
Secure Implementation of Stream Cipher: Trivium
Lecture Notes in Computer Science, 2015
Trivium is a hardware oriented synchronous stream cipher designed by Christophe De Canniere and B... more Trivium is a hardware oriented synchronous stream cipher designed by Christophe De Canniere and Bart Preneel [7]. Trivium is one of the eSTREAM final portfolio cipher. Regardless of the security of the cipher in theory, implementation attacks like Differential Power Analysis (DPA) attack [10, 12, 18] and Fault attack [9] on Trivium were observed. DPA attack of Trivium exploits the re-synchronization phase of the algorithm to reveal the key.
Over a decade, cryptographers are more attentive on designing lightweight ciphers in focus to com... more Over a decade, cryptographers are more attentive on designing lightweight ciphers in focus to compact cryptographic devices. More often, the security of these algorithms are defined in terms of its resistance to mathematical cryptanalysis methods. Nevertheless, designers are well aware of implementation attacks and concentrating on new design strategies to improve the defence quality against implementation attack. PRINCE [3] and RECTANGLE [17] lightweight block ciphers are designed using new design strategies for efficiency and security. In this paper we analyse the security of PRINCE and RECTANGLE against a type of implementation attack called Differential Power Analysis (DPA) attack. Our attack reduces key search space from 2 128 to 33008 for PRINCE and 2 80 to 288 for RECTANGLE.

Vulnerability Analysis of PRINCE and RECTANGLE using CPA
Proceedings of the 1st ACM Workshop on Cyber-Physical System Security, 2015
As Internet of Things (IoT) evolves very rapidly, security components (cryptographic algorithm, p... more As Internet of Things (IoT) evolves very rapidly, security components (cryptographic algorithm, protocol) of embedded devices need to be secure against software and physical attacks. However, the performance factors namely speed, area, and power play a major role in selection of security components for a resource constrained embedded devices. Subsequently, cryptographers are more attentive on designing lightweight ciphers to protect the information in such devices. PRINCE and RECTANGLE lightweight block ciphers are proposed using new design strategies for efficiency and security. In this paper we analyse the security of PRINCE and RECTANGLE against a type of side-channel attack called Correlation Power Analysis (CPA) attack. Our attack reduces key search space from 2128 to 33008 for PRINCE and 280 to 288 for RECTANGLE.

Lecture Notes in Computer Science, 2014
Power analysis attack is one of the most important and effective side channel attack methods, tha... more Power analysis attack is one of the most important and effective side channel attack methods, that has been attempted against implementations of cryptographic algorithms. In this paper, we investigate the vulnerability of SIMON [5] and LED [16] lightweight block ciphers against Differential Power Analysis (DPA) attack. Firstly, we describe the power model used to mount the attack on Field Programmable Gate Array (FPGA) implementation of SIMON and LED block ciphers. Then, we proceed to experimentally verified DPA attack, which is the first successful DPA attack on the algorithms. Our attack retrieves complete 64-bit key of SIMON32/64 and LED-64 with a complexity of 176 and 2 18 hypotheses respectively. Finally, we present our analysis on other versions of SIMON and LED. Our DPA results exhibits the weakness of algorithms, which emphasize the need for secure implementation of SIMON and LED.
Robust message authentication in the context of quantum key distribution
International Journal of Information and Computer Security

Crypto Primitives IPCore Implementation Susceptibility in Cyber Physical System
2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS), 2018
Security evaluation of third-party cryptographic Soft/Hard IP (Intellectual Property) core is oft... more Security evaluation of third-party cryptographic Soft/Hard IP (Intellectual Property) core is often ignored due to several reasons including, lack of awareness about its adversity, lack of knowledge about validation methodology or considering security as a byproduct. Particularly, the security validation of bought-out Hardware IP core is important before being deployed in particle means. In this paper, we present Look-Up-Table (LUT) based unrolled implementation of low latency cipher, PRINCE as an hard IP core and show how the susceptible implementation (nested and flexible placement of IP cores) can be experimentally exploited to reveal secret key in FPGA using power analysis attack. Such vulnerability in constrained devices, Internet-of-Things(IoT), causes serious threats in cyber physical system.
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Papers by Dillibabu Shanmugam